Difference between revisions of "intel/xeon gold/6161"

	Edit Values
	Xeon Gold 6161
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	6161
Market	Server
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6100
Locked	Yes
Frequency	2,200 MHz
Turbo Frequency	Yes
Turbo Frequency	3,000 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	22
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Purley
Chipset	Lewisburg
Core Name	Skylake SP
Core Family	6
Core Stepping	H0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	22
Threads	44
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
	Electrical
TDP	165 W
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Latest revision as of 00:15, 24 May 2019

Xeon Gold 6161 is a 64-bit x86 high-performance server docosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6161 operates at 2.2 GHz with a TDP of 165 W and a turbo frequency of 3 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.375 MiB

1,408 KiB
1,441,792 B

L1I$	704 KiB 720,896 B 0.688 MiB	22x32 KiB	8-way set associative
L1D$	704 KiB 720,896 B 0.688 MiB	22x32 KiB	8-way set associative	write-back

L2$

22 MiB

22,528 KiB
23,068,672 B
0.0215 GiB

		22x1 MiB	16-way set associative	write-back

L3$

30.25 MiB

30,976 KiB
31,719,424 B
0.0295 GiB

		22x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Controllers	1
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
EIST	Enhanced SpeedStep Technology
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
SMEP	OS Guard Technology

@@ Line 13: / Line 13: @@
 |frequency=2,200 MHz
 |turbo frequency1=3,000 MHz
+|turbo frequency=Yes
 |bus type=DMI 3.0
 |bus links=4
@@ Line 37: / Line 38: @@
 |temp min=<!-- use TJ/TC whenever possible instead -->
 |tjunc min=<!-- .. °C -->
+|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
 |package name 1=intel,fclga_3647
-|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
-|turbo frequency=Yes
 }}
 '''Xeon Gold 6161''' is a {{arch|64}} [[x86]] high-performance server [[docosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6161 operates at 2.2 GHz with a TDP of 165 W and a {{intel|Turbo Boost|turbo frequency}} of 3 GHz.

base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	22 +
core count	22 +
core family	6 +
core name	Skylake SP +
core stepping	H0 +
designer	Intel +
family	Xeon Gold +
full page name	intel/xeon gold/6161 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard +
has intel enhanced speedstep technology	true +
has intel supervisor mode execution protection	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,408 KiB (1,441,792 B, 1.375 MiB) +
l1d$ description	8-way set associative +
l1d$ size	704 KiB (720,896 B, 0.688 MiB) +
l1i$ description	8-way set associative +
l1i$ size	704 KiB (720,896 B, 0.688 MiB) +
l2$ description	16-way set associative +
l2$ size	22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
l3$ description	11-way set associative +
l3$ size	30.25 MiB (30,976 KiB, 31,719,424 B, 0.0295 GiB) +
ldate	3000 +
manufacturer	Intel +
market segment	Server +
max cpu count	4 +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Skylake (server) +
model number	6161 +
name	Xeon Gold 6161 +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
series	6100 +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	165 W (165,000 mW, 0.221 hp, 0.165 kW) +
technology	CMOS +
thread count	44 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +

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Latest revision as of 00:15, 24 May 2019

Cache[edit]

Memory controller[edit]

Features[edit]