Semiconductor & Computer Engineering
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=== Block Diagram === | === Block Diagram === | ||
==== Typical SoC ==== | ==== Typical SoC ==== | ||
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| + | The Neoverse N1 is also expected to be integrated along with {{\\|Neoverse E1}} high-efficiency cores and possibly other custom IP blocks. | ||
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| + | :[[File:neoverse e1 n1 soc example.svg|750px]] | ||
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==== Individual Core ==== | ==== Individual Core ==== | ||
:[[File:neoverse n1 block diagram.svg|850px]] | :[[File:neoverse n1 block diagram.svg|850px]] | ||
Revision as of 12:07, 20 February 2019
| Edit Values | |
| Ares µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | February 20, 2019 |
| Process | 7 nm |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
Neoverse N1 (codename Ares) is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
History
Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019.
Release Dates
Ares was officially disclosed on February 20, 2019.
Process Technology
Ares specifically takes advantage of the power and area advantages of the 7 nm process.
Architecture
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
This list is incomplete; you can help by expanding it.
Block Diagram
Typical SoC
The Neoverse N1 is also expected to be integrated along with Neoverse E1 high-efficiency cores and possibly other custom IP blocks.
Individual Core
Die
N1 core
- 7 nm process
- 1 Core + L2
- 1.2 mm² die size (1C + 512 KiB L2)
- 1.4 mm² die size (1C + 1 MiB L2)
- 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 W (1.0 V)
Bibliography
- Drew Henry keynote, TechCon 2018 keynote.
- Drew Henry, direct communication
- Most of the technical details were obtained directly from Arm
| codename | Neoverse N1 + |
| core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
| designer | ARM Holdings + |
| first launched | February 20, 2019 + |
| full page name | arm holdings/microarchitectures/neoverse n1 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Neoverse N1 + |
| pipeline stages | 11 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |