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Difference between revisions of "arm holdings/microarchitectures/poseidon"
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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=Poseidon |
|designer=ARM Holdings | |designer=ARM Holdings | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
+ | |introduction=2021 | ||
|process 2=5 nm | |process 2=5 nm | ||
|oooe=Yes | |oooe=Yes |
Revision as of 17:20, 15 December 2018
Edit Values | |
Poseidon µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | 2021 |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Succession | |
Poseidon is the successor to Zeus, a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
History
Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
Release Dates
Ares is expected to show up in products around 2021.
Process Technology
Zeus specifically designed takes advantage of the power and area advantages of the 5nm process.
Architecture
Key changes from Zeus
- 5 nm process (from 7nm)
This list is incomplete; you can help by expanding it.
Bibliography
- Drew Henry keynote, TechCon 2018 keynote.
Facts about "Poseidon - Microarchitectures - ARM"
codename | Poseidon + |
designer | ARM Holdings + |
first launched | 2021 + |
full page name | arm holdings/microarchitectures/poseidon + |
instance of | microarchitecture + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Poseidon + |
process | 5 nm (0.005 μm, 5.0e-6 mm) + |