Semiconductor & Computer Engineering
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Difference between revisions of "arm holdings/microarchitectures/neoverse n1"
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|designer=ARM Holdings | |designer=ARM Holdings | ||
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|process=10 nm | |process=10 nm | ||
|process 2=7 nm | |process 2=7 nm | ||
Revision as of 17:21, 15 December 2018
| Edit Values | |
| Ares µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 10 nm, 7 nm |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
Ares is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
History
Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares is expected to be a new core specifically designed with higher and power for the server market.
Release Dates
Ares is expected to show up in products in 2019.
Process Technology
Ares specifically takes advantage of the power and area advantages of the 7 nm process.
Architecture
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
This list is incomplete; you can help by expanding it.
Bibliography
- Drew Henry keynote, TechCon 2018 keynote.
Facts about "Neoverse N1 - Microarchitectures - ARM"
| codename | Ares + |
| designer | ARM Holdings + |
| first launched | 2019 + |
| full page name | arm holdings/microarchitectures/neoverse n1 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Ares + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |