From WikiChip
Difference between revisions of "arm holdings/microarchitectures/neoverse n1"
< arm holdings

Line 10: Line 10:
 
|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
 +
|predecessor=Cortex-A75
 +
|predecessor link=arm_holdings/microarchitectures/cortex-a75
 +
|successor=Zeus
 +
|successor link=arm_holdings/microarchitectures/zeus
 
}}
 
}}
 
'''Ares''' is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
'''Ares''' is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.

Revision as of 00:47, 14 December 2018

Edit Values
Ares µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Process10 nm, 7 nm
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Succession

Ares is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
codenameAres +
designerARM Holdings +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameAres +
process10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +