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Although 64-bit [[ARM]] {{arm|registers}} are 64-bit wide, virtual addresses require that the top 16 bits must either be <code>0x0000</code> or <code>0xFFFF</code>. TBI is a hardware feature, introduced with [[AArch64]], that allows software to use 8 most [[significant bits]] of a 64-bit [[tagged pointer|pointer as a tag]]. This is done by enabling [[memory tagging]] support in the {{arm|Translation Control Register}}. When enabled, the top eight bits ([63:56]) of the [[virtual address]] are ignored. | Although 64-bit [[ARM]] {{arm|registers}} are 64-bit wide, virtual addresses require that the top 16 bits must either be <code>0x0000</code> or <code>0xFFFF</code>. TBI is a hardware feature, introduced with [[AArch64]], that allows software to use 8 most [[significant bits]] of a 64-bit [[tagged pointer|pointer as a tag]]. This is done by enabling [[memory tagging]] support in the {{arm|Translation Control Register}}. When enabled, the top eight bits ([63:56]) of the [[virtual address]] are ignored. | ||
| + | == See also == | ||
| + | * ARM's {{arm|MTE}} | ||
{{stub}} | {{stub}} | ||
[[category:arm]] | [[category:arm]] | ||
Revision as of 13:28, 8 December 2018
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Top-byte ignore (TBI) is a feature introduced with ARMv8 that provides facilities for memory tagging by ignoring the most significant 8 bits of the virtual address.
Overview
Although 64-bit ARM registers are 64-bit wide, virtual addresses require that the top 16 bits must either be 0x0000 or 0xFFFF. TBI is a hardware feature, introduced with AArch64, that allows software to use 8 most significant bits of a 64-bit pointer as a tag. This is done by enabling memory tagging support in the Translation Control Register. When enabled, the top eight bits ([63:56]) of the virtual address are ignored.
See also
- ARM's MTE
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