Revision as of 11:56, 12 November 2018

Zen 2 is a planned microarchitecture being developed by AMD as a successor to Zen+. Zen 2 is expected to be succeeded by Zen 3.

History

Zen 2 is set to succeed Zen in the future, sometimes around 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later Zen 3. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize 7 nm process.

Codenames

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Process technology

Zen 2 is fabricated on TSMC's 7 nm process.

Compiler support

• Note: Initial support in GCC 9.

Architecture

Nothing concrete is currently known about the architectural improvements that is being done to Zen 2. Papermaster's presentation at Next Horizon quotes "Improved Branch Predictor", "Better Instruction Pre-Fetching", "Re-Optimized Instruction Cache", "Larger Op Cache", "Doubled Floating Point Width to 256-bit", "Doubled Load / Store Bandwidth", "Increased Dispatch / Retire Bandwidth", "Maintained High Throughput for All Modes" without further specifics.

Key changes from Zen

• 7 nm process (from 14 nm)
• PCIe 4.0 (from 3.0)

This list is incomplete; you can help by expanding it.

New instructions

Zen 2 introduced a number of new x86 instructions:

• CLWB - Force cache line write-back without flush
• RDPID - Read Processor ID
• WBNOINVD - Force cache line write-back without invalidation

Bibliography

• AMD 'Tech Day', February 22, 2017
• AMD 2017 Financial Analyst Day, May 16, 2017
• AMD GCC 9 znver2 enablement patch
• AMD 'Next Horizon', November 6, 2018

See Also

• Intel Ice Lake