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Difference between revisions of "amd/microarchitectures/zen 2"
(Updated "Rome" max core / thread count with information provided on November 6 2018 from AMD's Next Horizon event also added Next Horizon to Bibliography) |
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=== Key changes from {{\\|Zen}} === | === Key changes from {{\\|Zen}} === | ||
* [[7 nm process]] (from [[14 nm]]) | * [[7 nm process]] (from [[14 nm]]) | ||
| + | * PCIe 4.0 (from 3.0) | ||
{{expand list}} | {{expand list}} | ||
Revision as of 18:26, 6 November 2018
| Edit Values | |
| Zen 2 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 7 nm |
| Succession | |
Zen 2 is a planned microarchitecture being developed by AMD as a successor to Zen+. Zen 2 is expected to be succeeded by Zen 3.
Contents
History
Zen 2 is set to succeed Zen in the future, sometimes around 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later Zen 3. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize 7 nm process.
Codenames
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Core | C/T | Target |
|---|---|---|
| Rome | Up to 64/128 | High-end server multiprocessors |
| Castle Peak | ?/? | workstation & enthusiasts market processors |
| Matisse | ?/? | Mainstream to high-end desktops & enthusiasts market processors |
| Picasso | ?/? | Mainstream desktop & mobile processors with GPU |
Process technology
Zen 2 is fabricated on TSMC's 7 nm process.
Architecture
Nothing is currently known about the architectural improvements that is being done to Zen 2.
Key changes from Zen
- 7 nm process (from 14 nm)
- PCIe 4.0 (from 3.0)
This list is incomplete; you can help by expanding it.
New instructions
Zen 2 introduced a number of new x86 instructions:
-
CLWB- Force cache line write-back without flush -
RDPID- Read Processor ID -
WBNOINVD- Force cache line write-back without invalidation
Bibliography
- AMD 'Tech Day', February 22, 2017
- AMD 2017 Financial Analyst Day, May 16, 2017
- AMD GCC 9 znver2 enablement patch
- AMD 'Next Horizon', November 6, 2018
See Also
- Intel Ice Lake
Facts about "Zen 2 - Microarchitectures - AMD"
| codename | Zen 2 + |
| core count | 4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 64 + |
| designer | AMD + |
| first launched | July 2019 + |
| full page name | amd/microarchitectures/zen 2 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | TSMC + and GlobalFoundries + |
| microarchitecture type | CPU + |
| name | Zen 2 + |
| pipeline stages | 19 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) +, 12 nm (0.012 μm, 1.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |