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Difference between revisions of "apm/x-gene/apm883408-x1"
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'''APM883408-X1''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2012]]. Fabricated on [[TSMC]] [[40 nm process]] based on the {{apm|Storm|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of quad-channel DDR3-1866 memory. | '''APM883408-X1''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2012]]. Fabricated on [[TSMC]] [[40 nm process]] based on the {{apm|Storm|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of quad-channel DDR3-1866 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|apm/microarchitectures/storm#Memory_Hierarchy|l1=Storm § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=512 KiB | ||
+ | |l1i cache=256 KiB | ||
+ | |l1i break=8x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=256 KiB | ||
+ | |l1d break=8x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=Write-through with write-combine | ||
+ | |l2 cache=1 MiB | ||
+ | |l2 break=4x256 KiB | ||
+ | |l3 cache=8 MiB | ||
+ | |l3 break=1x8 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-1866 | ||
+ | |ecc=Yes | ||
+ | |max mem=256 GiB | ||
+ | |controllers=1 | ||
+ | |channels=4 | ||
+ | |max bandwidth=55.63 GiB/s | ||
+ | |bandwidth schan=13.91 GiB/s | ||
+ | |bandwidth dchan=27.82 GiB/s | ||
+ | |bandwidth qchan=55.63 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=17 | ||
+ | |pcie config=1x16+x1 | ||
+ | |pcie config 2=2x8+x1 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=USB | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=2 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=SATA | ||
+ | |sata revision=3.0 | ||
+ | |sata ports=6 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | * 2x I2C | ||
+ | * 4x UARTs | ||
+ | * GPIOs | ||
+ | * 2x SPI | ||
+ | * 2x SDIO 3.0 | ||
+ | * JTAG / Trace | ||
+ | |||
+ | === Network === | ||
+ | {{network}} |
Revision as of 21:37, 25 September 2018
Edit Values | |
APM883408-X1 | |
General Info | |
Designer | AppliedMicro |
Manufacturer | TSMC |
Model Number | APM883408-X1 |
Market | Server |
Introduction | October 28, 2011 (announced) 2012 (launched) |
General Specs | |
Family | X-Gene |
Series | X-Gene 1 |
Turbo Frequency | 2,400 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Storm |
Core Name | Potenza |
Process | 40 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 256 GiB |
Electrical | |
Vcore | 0.9 V |
VI/O | 1.8 V, 2.5 V |
Tjunction | 0 °C – 90 °C |
APM883408-X1 is a 64-bit octa-core ARM server microprocessor designed by AppliedMicro and introduced in 2012. Fabricated on TSMC 40 nm process based on the Storm microarchitecture, this processor has eight custom ARMv8 cores operating at up to 2.4 GHz and supporting up to 256 GiB of quad-channel DDR3-1866 memory.
Cache
- Main article: Storm § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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- 2x I2C
- 4x UARTs
- GPIOs
- 2x SPI
- 2x SDIO 3.0
- JTAG / Trace
Network
Networking
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Facts about "X-Gene 1 APM883408-X1 - AppliedMicro"
core count | 8 + |
core name | Potenza + |
core voltage | 0.9 V (9 dV, 90 cV, 900 mV) + |
designer | AppliedMicro + |
family | X-Gene + |
first announced | October 28, 2011 + |
first launched | 2012 + |
full page name | apm/x-gene/apm883408-x1 + |
instance of | microprocessor + |
io voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) + and 2.5 V (25 dV, 250 cV, 2,500 mV) + |
isa | ARMv8 + |
isa family | ARM + |
ldate | 2012 + |
manufacturer | TSMC + |
market segment | Server + |
max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
max memory | 262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) + |
microarchitecture | Storm + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | APM883408-X1 + |
name | APM883408-X1 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |
series | X-Gene 1 + |
technology | CMOS + |
thread count | 8 + |
turbo frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |