From WikiChip
Difference between revisions of "arm holdings/microarchitectures/cortex-a75"
< arm holdings

Line 38: Line 38:
 
}}
 
}}
 
'''Cortex-A75''' (codename '''Prometheus''') is the successor to the {{armh|Cortex-A73|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
 
'''Cortex-A75''' (codename '''Prometheus''') is the successor to the {{armh|Cortex-A73|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
 +
 +
== Compiler support ==
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[Arm Compiler]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
 +
|-
 +
| [[GCC]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
 +
|-
 +
| [[LLVM]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
 +
|}
 +
 +
If the Cortex-A75 is coupled with the {{\\|Cortex-A55}} in a [[big.LITTLE]] system, GCC also supports the following option:
 +
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Tune
 +
|-
 +
| [[GCC]] || <code>-mtune=cortex-a75.cortex-a55</code>
 +
|}

Revision as of 14:50, 31 December 2018

Edit Values
Cortex-A75 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionMay 29, 2017
Process16 nm, 14 nm, 10 nm, 7 nm
Core Configs1, 2
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages11-13
Decode3-way
Instructions
ISAARMv8.2
ExtensionsFPU, NEON
Cache
L1I Cache8-64 KiB/core
4-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256-512 KiB/core
L3 Cache0-4 MiB/Cluster
Succession

Cortex-A75 (codename Prometheus) is the successor to the Cortex-A73, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.

Compiler support

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a75 -mtune=cortex-a75
GCC -mcpu=cortex-a75 -mtune=cortex-a75
LLVM -mcpu=cortex-a75 -mtune=cortex-a75

If the Cortex-A75 is coupled with the Cortex-A55 in a big.LITTLE system, GCC also supports the following option:

Compiler Tune
GCC -mtune=cortex-a75.cortex-a55
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a75&oldid=85508"
Facts about "Cortex-A75 - Microarchitectures - ARM"
RDF feed
codenameCortex-A75 +
core count1 + and 2 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a75 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A75 +
pipeline stages (max)13 +
pipeline stages (min)11 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +