From WikiChip
Difference between revisions of "arm holdings/microarchitectures/neoverse n1"
< arm holdings

(ares)
 
Line 1: Line 1:
−
{{armh title|Cortex-A76 (Ares)|arch}}
+
{{armh title|Cortex-Ares|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Cortex-A76
+
|name=Cortex-Ares
 
|designer=ARM Holdings
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|introduction=May 31, 2018
 
 
|process=10 nm
 
|process=10 nm
 
|process 2=7 nm
 
|process 2=7 nm
−
|cores=1
 
−
|cores 2=2
 
−
|cores 3=4
 
 
|oooe=Yes
 
|oooe=Yes
 
|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
−
|stages min=11
 
−
|stages max=13
 
−
|decode=4-way
 
−
|isa=ARMv8.2
 
−
|feature=Hardware virtualization
 
−
|extension=FPU
 
−
|extension 2=NEON
 
−
|l1i=8-64 KiB
 
−
|l1i per=core
 
−
|l1i desc=4-way set associative
 
−
|l1d=8-64 KiB
 
−
|l1d per=core
 
−
|l1d desc=4-way set associative
 
−
|l2=64-256-512 KiB
 
−
|l2 per=core
 
−
|l3=0-4 MiB
 
−
|l3 per=Cluster
 
−
|predecessor=Cortex-A75
 
−
|predecessor link=arm holdings/microarchitectures/prometheus
 
−
|successor=Deimos
 
−
|successor link=arm holdings/microarchitectures/deimos
 
 
}}
 
}}
−
'''Cortex-A76''' (codename '''Ares''') is the successor to the {{armh|Cortex-A75|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
+
'''Ares''' is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 +
 
 +
 
 +
{{future information}}

Revision as of 16:40, 8 September 2018

Edit Values
Cortex-Ares µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Process10 nm, 7 nm
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes

Ares is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/neoverse_n1&oldid=82224"
Facts about "Neoverse N1 - Microarchitectures - ARM"
RDF feed
codenameNeoverse N1 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedFebruary 20, 2019 +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N1 +
pipeline stages11 +
process7 nm (0.007 μm, 7.0e-6 mm) +