Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "supercomputers/astra"
| Line 1: | Line 1: | ||
| − | {{sc title|Astra}} | + | {{sc title|Astra}}[[File:astra supercomputer illustration.png|thumb|right|class=wikichip_ogimage|Astra Illustration]] |
'''Astra''' is a [[petascale]] [[ARM]] supercomputer designed for [[Sandia National Laboratories]] expeced to be deployed in mid-[[2018]]. This is the first ARM-based supercomputer to exceed 1 [[petaFLOPS]]. | '''Astra''' is a [[petascale]] [[ARM]] supercomputer designed for [[Sandia National Laboratories]] expeced to be deployed in mid-[[2018]]. This is the first ARM-based supercomputer to exceed 1 [[petaFLOPS]]. | ||
| + | |||
| + | == History == | ||
| + | Astra is an [[ARM]]-based supercomputer expected to be deployed at [[Sandia National Laboratories]]. The computer is one of a series of prototypes commissioned by the [[U.S. Department of Energy]] as part of a program that evaluates the feasibility of emerging high-performance computing architectures as production platforms to support NNSA's mission. | ||
== Overview == | == Overview == | ||
| − | Astra is | + | Astra is the first [[ARM]]-based petascale supercomputer. The system consists of 5,184 [[Cavium]] [[ThunderX2 CN9975]] processors with a 1.2 MW power consumption for a peak performance of 2.322 [[petaFLOPS]]. Each [[ThunderX2 CN9975]] has [[28 cores]] operating at 2 GHz. There are also 108 36-port switches and 3 540-port spine switches. |
| + | |||
| + | <table class="wikitable"> | ||
| + | <tr><th></th><td>Components</td></tr> | ||
| + | <tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td></tr> | ||
| + | <tr><th>Racks</th><td>36</td></tr> | ||
| + | <tr><th>Peak FLOPS</th><td>2.322 petaFLOPS</td></tr> | ||
| + | </table> | ||
| + | |||
| + | Astra has close around 700 [[terabytes]] of memory. | ||
| + | |||
| + | <table class="wikitable"> | ||
| + | <tr><th colspan="4">Astra Total Memory</th></tr> | ||
| + | <tr><th>Type</th><td>[[DDR4]]</td><td>[[NVMe]]</td><tr> | ||
| + | <tr><th>Node</th><td>128 GiB</td><td>?</td></tr> | ||
| + | <tr><th>Astra</th><td>324 TiB</td><td>403 TB</td></tr> | ||
| + | </table> | ||
| + | |||
| + | == Architecture == | ||
| + | {{empty section}} | ||
| + | === System === | ||
| + | {{empty section}} | ||
| + | === Compute Rack === | ||
| + | {{empty section}} | ||
| + | === Compute Node === | ||
| + | {{empty section}} | ||
| + | ==== Socket ==== | ||
| + | {{empty section}} | ||
| + | ==== Full-node ==== | ||
| + | {{empty section}} | ||
== Bibliography == | == Bibliography == | ||
Revision as of 21:56, 12 August 2018
Astra is a petascale ARM supercomputer designed for Sandia National Laboratories expeced to be deployed in mid-2018. This is the first ARM-based supercomputer to exceed 1 petaFLOPS.
Contents
History
Astra is an ARM-based supercomputer expected to be deployed at Sandia National Laboratories. The computer is one of a series of prototypes commissioned by the U.S. Department of Energy as part of a program that evaluates the feasibility of emerging high-performance computing architectures as production platforms to support NNSA's mission.
Overview
Astra is the first ARM-based petascale supercomputer. The system consists of 5,184 Cavium ThunderX2 CN9975 processors with a 1.2 MW power consumption for a peak performance of 2.322 petaFLOPS. Each ThunderX2 CN9975 has 28 cores operating at 2 GHz. There are also 108 36-port switches and 3 540-port spine switches.
| Components | |
| Processors | 5,184 2 x 72 x 36 |
| Racks | 36 |
| Peak FLOPS | 2.322 petaFLOPS |
Astra has close around 700 terabytes of memory.
| Astra Total Memory | |||
|---|---|---|---|
| Type | DDR4 | NVMe | |
| Node | 128 GiB | ? | |
| Astra | 324 TiB | 403 TB | |
Architecture
 |
This section is empty; you can help add the missing info by editing this page. |
System
| |
This section is empty; you can help add the missing info by editing this page. |
Compute Rack
| |
This section is empty; you can help add the missing info by editing this page. |
Compute Node
| |
This section is empty; you can help add the missing info by editing this page. |
Socket
| |
This section is empty; you can help add the missing info by editing this page. |
Full-node
| |
This section is empty; you can help add the missing info by editing this page. |
Bibliography
- SNL (personal communication, August 2018).
- DOE. (June 18, 2018). "Arm-based supercomputer prototype to be deployed at Sandia National Laboratories" [Press Release]
- Kevin Pedretti, Jim H. Laros III, Si Hammond. (June 28, 2018). "Vanguard Astra: Maturing the ARM Software Ecosystem for U.S. DOE/ASC Supercomputing"