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Difference between revisions of "amd/cpuid"
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| rowspan="5" | {{amd|Zen|l=arch}} || {{amd|Raven Ridge|l=core}} || 0x8 || 0xF || 0x1 || 0x1 || [[Family 23 Model 17]] | | rowspan="5" | {{amd|Zen|l=arch}} || {{amd|Raven Ridge|l=core}} || 0x8 || 0xF || 0x1 || 0x1 || [[Family 23 Model 17]] | ||
|- | |- | ||
| − | | {{amd|Naples|l=core}}, {{amd|Whitehaven|l=core}}, {{amd|Summit Ridge|l=core}} || 0x8 || 0xF || 0x0 || 0x1 || [[Family 23 Model 1]] | + | | {{amd|Naples|l=core}}, {{amd|Whitehaven|l=core}}, {{amd|Summit Ridge|l=core}}, {{amd|Snowy Owl|l=core}} || 0x8 || 0xF || 0x0 || 0x1 || [[Family 23 Model 1]] |
|} | |} | ||
[[category:amd]][[category:x86]] | [[category:amd]][[category:x86]] | ||
Revision as of 16:06, 10 September 2018
x86
Instruction Set Architecture
Instruction Set Architecture
General
Variants
Topics
- Instructions
- Addressing Modes
- Registers
- Model-Specific Register
- Assembly
- Interrupts
- Micro-Ops
- Timer
- Calling Convention
- Microarchitectures
- CPUID
CPUIDs
- AMD's CPUIDs
- Intel's CPUIDs
Modes
Extensions(all)
Below is a list of AMD's CPUID broken down by their respective core names and microarchitecture:
This article is a work in progress!CPUIDs
Family 23
| Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
|---|---|---|---|---|---|---|
| Zen 3 | ||||||
| Zen 2 | Rome (?) | 0x8 | 0xF | 0x2 | 0x? | Family 23 Model [32-47] |
| Zen+ | Pinnacle Ridge | 0x8 | 0xF | 0x0 | 0x8 | Family 23 Model 8 |
| Zen | Raven Ridge | 0x8 | 0xF | 0x1 | 0x1 | Family 23 Model 17 |
| Naples, Whitehaven, Summit Ridge, Snowy Owl | 0x8 | 0xF | 0x0 | 0x1 | Family 23 Model 1 |