Semiconductor & Computer Engineering
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Difference between revisions of "hisilicon/kunpeng/hi1610"
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|max memory=256 GiB | |max memory=256 GiB | ||
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| − | '''Hi1610''' is a [[hexadeca-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in late-2015. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 16 {{armh|Cortex-A57}} cores operating at 2.1 GHz. The Hi1610 supports up to | + | '''Hi1610''' is a [[hexadeca-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in late-2015. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 16 {{armh|Cortex-A57}} cores operating at 2.1 GHz. The Hi1610 supports up to 128 GiB of dual-channel DDR4-1866 memory. |
== Cache == | == Cache == | ||
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|max mem=256 GiB | |max mem=256 GiB | ||
|controllers=1 | |controllers=1 | ||
| − | |channels= | + | |channels=2 |
|width=64 bit | |width=64 bit | ||
|max bandwidth=55.63 GiB/s | |max bandwidth=55.63 GiB/s | ||
|bandwidth schan=13.91 GiB/s | |bandwidth schan=13.91 GiB/s | ||
|bandwidth dchan=27.81 GiB/s | |bandwidth dchan=27.81 GiB/s | ||
| − | |||
}} | }} | ||
Revision as of 01:25, 1 August 2018
| Edit Values | |
| Hi1610 | |
| General Info | |
| Designer | HiSilicon, ARM Holdings |
| Manufacturer | TSMC |
| Model Number | Hi1610 |
| Market | Server |
| Introduction | 2015 (announced) 2015 (launched) |
| General Specs | |
| Family | Hi16xx |
| Frequency | 2,100 MHz |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Cortex-A57 |
| Core Name | Cortex-A57 |
| Process | 16 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 16 |
| Threads | 16 |
| Max Memory | 256 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
Hi1610 is a hexadeca-core 64-bit ARM server microprocessor introduced by HiSilicon in late-2015. Fabricated by TSMC on a 16 nm process, this chip incorporates 16 Cortex-A57 cores operating at 2.1 GHz. The Hi1610 supports up to 128 GiB of dual-channel DDR4-1866 memory.
Cache
- Main article: Cortex-A57 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Facts about "Hi1610 - HiSilicon"
| core count | 16 + |
| designer | HiSilicon + and ARM Holdings + |
| family | Hi16xx + |
| full page name | hisilicon/kunpeng/hi1610 + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| ldate | 1900 + |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 1 + |
| model number | Hi1610 + |
| name | Hi1610 + |
| smp max ways | 1 + |
| thread count | 16 + |
| word size | 64 bit (8 octets, 16 nibbles) + |