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Difference between revisions of "intel/cores/ice lake sp"
| Line 8: | Line 8: | ||
|isa family=x86 | |isa family=x86 | ||
|microarch=Ice Lake (server) | |microarch=Ice Lake (server) | ||
| + | |platform=Whitley | ||
|word=64 bit | |word=64 bit | ||
|proc=10 nm | |proc=10 nm | ||
|tech=CMOS | |tech=CMOS | ||
| − | |package | + | |package name 1=intel,fclga_4189 |
|predecessor=Cascade Lake SP | |predecessor=Cascade Lake SP | ||
|predecessor link=intel/cores/cascade lake sp | |predecessor link=intel/cores/cascade lake sp | ||
Revision as of 14:02, 10 June 2018
| Edit Values | |
| Ice Lake SP | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Ice Lake (server) |
| Platform | Whitley |
| Word Size | 8 octets 64 bit16 nibbles |
| Process | 10 nm 0.01 μm 1.0e-5 mm |
| Technology | CMOS |
| Packaging | |
| Package | FCLGA-4189 (LGA) |
| Contacts | 4189 |
| Socket | Socket W, LGA-4189 |
| Succession | |
Ice Lake SP (Ice Lake Scalable Performance) is the code name for Intel's series of server multiprocessors based on the Ice Lake microarchitecture as part of the Whitley platform serving as the successor to Cascade Lake SP.
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Facts about "Ice Lake SP - Cores - Intel"
| designer | Intel + |
| instance of | core + |
| isa | x86-64 + |
| isa family | x86 + |
| manufacturer | Intel + |
| microarchitecture | Ice Lake (server) + |
| name | Ice Lake SP + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |