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Difference between revisions of "intel/cores/ice lake sp"
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− | '''Ice Lake SP''' ('''{{intel|Ice Lake|l=arch}} Scalable Performance''') is the code name for Intel's series of server [[multiprocessors]] based on the {{intel|Ice Lake (server)|Ice Lake|l=arch}} microarchitecture as part of the {{intel| | + | '''Ice Lake SP''' ('''{{intel|Ice Lake|l=arch}} Scalable Performance''') is the code name for Intel's series of server [[multiprocessors]] based on the {{intel|Ice Lake (server)|Ice Lake|l=arch}} microarchitecture as part of the {{intel|Whitley|l=platform}} platform serving as the successor to {{intel|Cascade Lake SP|l=core}}. |
{{future information}} | {{future information}} |
Revision as of 17:29, 9 April 2018
Edit Values | |
Ice Lake SP | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Ice Lake (server) |
Word Size | 8 octets 64 bit16 nibbles |
Process | 10 nm 0.01 μm 1.0e-5 mm |
Technology | CMOS |
Packaging | |
Template:packages/intel/fclga-4189 | |
Succession | |
Ice Lake SP (Ice Lake Scalable Performance) is the code name for Intel's series of server multiprocessors based on the Ice Lake microarchitecture as part of the Whitley platform serving as the successor to Cascade Lake SP.
Facts about "Ice Lake SP - Cores - Intel"
designer | Intel + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
manufacturer | Intel + |
microarchitecture | Ice Lake (server) + |
name | Ice Lake SP + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |