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Difference between revisions of "intel/microarchitectures/polaris"
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'''Polaris''' was a research [[microarchitecture]] designed by [[Intel]] [[Intel Labs|Labs]] demonstarting the theoretical capabilities of a [[many-core]] chip performing 1 [[trillion floating point operations]]. | '''Polaris''' was a research [[microarchitecture]] designed by [[Intel]] [[Intel Labs|Labs]] demonstarting the theoretical capabilities of a [[many-core]] chip performing 1 [[trillion floating point operations]]. | ||
| + | |||
| + | == History == | ||
| + | Polaris was originally presented at [[IEEE ISSCC]] 2007. It was a concept project designed to demonstrate the potential of integrating many processing elements on a single [[silicon chip]] enabled by [[Moore's Law]] in order to achieve a high [[trillion floating point operations]] throughput. Polaris was Intel's first public chip as a direct consequence of their {{intel|Tera-scale Computing Research Program}} and is the basis of Intel's later research projects which paved the way for Intel's {{intel|Many Integrated Cores}} (MIC) architecture and the {{intel|Xeon Phi}} [[many-core]] processor family. | ||
| + | |||
| + | |||
| + | :[[File:intel many-core timeline.png|700px]] | ||
| + | |||
| + | == Architecture == | ||
| + | * [[network on a chip]] (NoC) | ||
| + | * 80 cores ("tiles") | ||
| + | ** operating at 4 GHz | ||
| + | ** arranged as 10x8 2D {{intel|mesh}} | ||
| + | |||
| + | == Die == | ||
| + | === SoC === | ||
| + | * Package LGA-1248 | ||
| + | ** 14 layers | ||
| + | ** 343 signal pins | ||
| + | * [[65 nm process]] | ||
| + | ** 1 poly, 8 metal (Cu) layers | ||
| + | * 21.72 mm x 12.64 mm | ||
| + | ** 274.54 mm² die size | ||
| + | * 100,000,000 transistors | ||
| + | |||
| + | :[[File:intel polaris die.png|400px]] | ||
| + | |||
| + | === Tile === | ||
| + | * 1.5 mm x 2.0 mm | ||
| + | * 3 mm² die size | ||
| + | :[[File:intel polaris core.png|400px]] | ||
Revision as of 00:08, 9 April 2018
| Edit Values | |
| Polaris µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | February 2007 |
| Process | 65 nm |
| Core Configs | 80 |
| Pipeline | |
| Type | VLIW |
| Stages | 9 |
| Cache | |
| L1I Cache | 3 KiB/core |
| L1D Cache | 2 KiB/core |
| Succession | |
Polaris was a research microarchitecture designed by Intel Labs demonstarting the theoretical capabilities of a many-core chip performing 1 trillion floating point operations.
Contents
History
Polaris was originally presented at IEEE ISSCC 2007. It was a concept project designed to demonstrate the potential of integrating many processing elements on a single silicon chip enabled by Moore's Law in order to achieve a high trillion floating point operations throughput. Polaris was Intel's first public chip as a direct consequence of their Tera-scale Computing Research Program and is the basis of Intel's later research projects which paved the way for Intel's Many Integrated Cores (MIC) architecture and the Xeon Phi many-core processor family.
Architecture
- network on a chip (NoC)
- 80 cores ("tiles")
- operating at 4 GHz
- arranged as 10x8 2D mesh
Die
SoC
- Package LGA-1248
- 14 layers
- 343 signal pins
- 65 nm process
- 1 poly, 8 metal (Cu) layers
- 21.72 mm x 12.64 mm
- 274.54 mm² die size
- 100,000,000 transistors
Tile
- 1.5 mm x 2.0 mm
- 3 mm² die size
Facts about "Polaris - Microarchitectures - Intel"
| codename | Polaris + |
| core count | 80 + |
| designer | Intel + |
| first launched | February 2007 + |
| full page name | intel/microarchitectures/polaris + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Polaris + |
| pipeline stages | 9 + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |