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Difference between revisions of "intel/microarchitectures/tiger lake"
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| − | |predecessor=Ice Lake | + | |predecessor=Ice Lake (client) |
| − | |predecessor link=intel/microarchitectures/ice lake | + | |predecessor link=intel/microarchitectures/ice lake (client) |
|successor=Alder Lake | |successor=Alder Lake | ||
|successor link=intel/microarchitectures/alder lake | |successor link=intel/microarchitectures/alder lake | ||
Revision as of 01:04, 6 April 2018
| Edit Values | |
| Tiger Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
| Contemporary | |
| Sapphire Rapids | |
Tiger Lake (TGL) is Intel's successor to Ice Lake, an enhanced 10nm++ process microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
- Main article: Cannon Lake § Process Technology
Tiger Lake is expected to be manufactured on Intel's third generation enhanced 10nm++ process.
Architecture
Not much is known about Tiger Lake's architecture.
Key changes from Ice Lake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |