Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/tiger lake"
| Line 16: | Line 16: | ||
|succession=Yes | |succession=Yes | ||
}} | }} | ||
| − | ''' | + | '''Tiger Lake''' ('''TGL''') is [[Intel]]'s successor to {{\\|Ice Lake (client)|Ice Lake}}, an enhanced [[10 nm process|10nm+ process]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. |
== Process Technology== | == Process Technology== | ||
Revision as of 22:49, 5 April 2018
| Edit Values | |
| Tigerlake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
| Contemporary | |
| Sapphire Rapids | |
Tiger Lake (TGL) is Intel's successor to Ice Lake, an enhanced 10nm+ process microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
- Main article: Cannon Lake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannon Lake.
Architecture
Not much is known about Tigerlake's architecture.
Key changes from Icelake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
See also
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| core count | 2 +, 4 +, 6 + and 8 + |
| designer | Intel + |
| first launched | September 2, 2020 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |