From WikiChip
Difference between revisions of "intel/microarchitectures/tremont"
< intel‎ | microarchitectures

(Architecture)
(Technology)
Line 40: Line 40:
  
 
== Technology ==
 
== Technology ==
{{empty section}}
+
Tremont appear to be planned for Intel's [[10 nm process]].
  
 
== Architecture ==
 
== Architecture ==

Revision as of 17:00, 4 April 2018

Edit Values
Tremont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2018/2019
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
Cores
Core NamesGemini Lake
Succession

Tremont is Intel's successor to Goldmont Plus, an ultra-low power microarchitecture for low-power devices and microservers.

Codenames

New text document.svg This section is empty; you can help add the missing info by editing this page.

Brands

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates

New text document.svg This section is empty; you can help add the missing info by editing this page.

Technology

Tremont appear to be planned for Intel's 10 nm process.

Architecture

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Goldmont Plus

New text document.svg This section is empty; you can help add the missing info by editing this page.

New instructions

Termont introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • ENCLV - SGX oversubscription instructions
  • CLDEMOTE - Cache line demote instruction
  • SSE_GFNI - SSE-based Galois Field New Instructions
  • Direct store instructions: MOVDIRI, MOVDIR64B
  • User wait instructions: TPAUSE, UMONITOR, UMWAIT
  • Split Lock Detection - detection and cause an exception for split locks