Revision as of 08:36, 29 June 2018

Ivy Bridge (IVB) was Intel's microarchitecture based on the 22 nm process for desktops and servers. Ivy Bridge was introduced in 2011 as a process shrink of Sandy Bridge which introduced a number of enhancements. Ivy Bridge became Intel's first microarchitecture to use tri-gate transistors for their commercial products.

For desktop and mobile, Ivy Bridge is branded as 3rd Generation Intel Core processors. For server class processors, Intel branded it as Xeon E3 v2, Xeon E5 v2, and Xeon E7 v2.

Codenames

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Process Technology

Ivy Bridge is designed to be manufactured using 22 nm Tri-gate FinFET transistors. This is Intel's first generation of FinFET. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high performance and high density respectively.

Scaling:

	Sandy Bridge	Ivy Bridge	Δ
	32 nm	22 nm
Fin Pitch	N/A	60 nm	N/A
Fin Width​		8 nm
Fin Height​		34 nm
Gate Pitch	112.5 nm	90 nm	0.80x
Interconnect Pitch	112.5 nm	80 nm	0.71x

Architecture

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Key changes from Sandy Bridge

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New instructions

Ivy Bridge introduced a number of new instructions:

• F16C - Extension for performing HP-SP conversions
• RDRAND - Secure Key Technology extension
• FS/GS base access

Block Diagram

Client SoC

Individual Core

Die

Quad-core Ivy Bridge die

• 1,480,000,000 transistors
• 160 mm²
• 4 CPU cores
• 1 GPU core
  • 2x8xEU (64 ALUs)
• 22 nm process

Hexa-core Ivy Bridge Die

• Core i7-4960X
• 1,860,000,000 transistors
• 256.5 mm²
• 15.0 mm x 17.1 mm
• 6 CPU cores
• 22 nm process

Deca-core Ivy Bridge Die

• 341 mm²
• 10 CPU cores
• 22 nm process

Pentadeca-Core Ivy Bridge die

• 541 mm²
• 4,310,000,000 transistors
• 15 CPU cores
• 22 nm process

Cores

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All Ivy Bridge Chips