Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "ampere computing/microarchitectures/quicksilver"
m (David moved page ampere computing/microarchitectures/shadowcat to ampere computing/microarchitectures/quicksilver without leaving a redirect) |
|
(No difference)
| |
Revision as of 02:39, 9 February 2018
| Edit Values | |
| Quicksilver µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Ampere Computing |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 7 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | ARMv8.2 |
| Succession | |
Retrieved from "https://en.wikichip.org/w/index.php?title=ampere_computing/microarchitectures/quicksilver&oldid=74112"
Facts about "Quicksilver - Microarchitectures - Ampere"
| codename | Quicksilver + |
| designer | Ampere Computing + |
| first launched | 2019 + |
| full page name | ampere computing/microarchitectures/quicksilver + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Quicksilver + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |