From WikiChip
Difference between revisions of "samsung/microarchitectures/m3"
< samsung

(m3)
 
Line 27: Line 27:
 
'''Mongoose 3''' ('''M3''') is an [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics serving as a successor to the {{\\|Mongoose 2}}.
 
'''Mongoose 3''' ('''M3''') is an [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics serving as a successor to the {{\\|Mongoose 2}}.
  
 +
== Process Technology ==
 +
The M3 was fabricated on Samsung's second generation [[10 nm process|10LPP (Low Power Plus) process]].
  
 +
== Compiler support ==
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[GCC]] || <code>-march=armv8-a+crypto</code> || <code>-mtune=exynos-m3</code>
 +
|}
 +
 +
== Architecture ==
 
{{future information}}
 
{{future information}}
 +
=== Key changes from {{\\|Mongoose 1}}/{{\\|Mongoose 2|M2}} ===
 +
* [[10 nm|10nm 10LPP process]] (from 1st gen 10LPP)
 +
* Core
 +
** Front-end
 +
*** larger [[instruction queue]] (40 entries, up from 24)
 +
*** 6-way decode (from 4)
 +
*** µOP fusion
 +
**** Can fuse address generation and memory operations
 +
**** Can fuse literal generation operations
 +
** Back-end
 +
*** larger [[ReOrder buffer]] (228 entries, from 96 entries)
 +
*** Has a fastpath logical shift of up to 3 places
 +
<!--
 +
*** Paired 128 bit loads and stores are no longer slow
 +
-->
 +
* branch misprediction penalty increased (16, from 14)
 +
 +
{{expand list}}

Revision as of 02:33, 5 February 2018

Edit Values
Mongoose 3 µarch
General Info
Arch TypeCPU
DesignerSamsung
ManufacturerSamsung
Process10 nm
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Decode6-way
Instructions
ISAARMv8
Cache
L1I Cache64 KiB/core
4-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache2 MiB/cluster
16-way set associative
Succession

Mongoose 3 (M3) is an ARM microarchitecture designed by Samsung for their consumer electronics serving as a successor to the Mongoose 2.

Process Technology

The M3 was fabricated on Samsung's second generation 10LPP (Low Power Plus) process.

Compiler support

Compiler Arch-Specific Arch-Favorable
GCC -march=armv8-a+crypto -mtune=exynos-m3

Architecture

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Mongoose 1/M2

  • 10nm 10LPP process (from 1st gen 10LPP)
  • Core
    • Front-end
      • larger instruction queue (40 entries, up from 24)
      • 6-way decode (from 4)
      • µOP fusion
        • Can fuse address generation and memory operations
        • Can fuse literal generation operations
    • Back-end
      • larger ReOrder buffer (228 entries, from 96 entries)
      • Has a fastpath logical shift of up to 3 places
  • branch misprediction penalty increased (16, from 14)

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/microarchitectures/m3&oldid=73703"
Facts about "Exynos M3 - Microarchitectures - Samsung"
RDF feed
codenameMongoose 3 +
designerSamsung +
full page namesamsung/microarchitectures/m3 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerSamsung +
microarchitecture typeCPU +
nameMongoose 3 +
process10 nm (0.01 μm, 1.0e-5 mm) +