Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/duron/d650ast1b"
m (Bot: switching template from {{mpu}} to a more generic {{chip}}) |
|||
| Line 1: | Line 1: | ||
{{amd title|Duron 650 (Spitfire)}} | {{amd title|Duron 650 (Spitfire)}} | ||
| − | {{ | + | {{mpu |
| name = Duron 650 | | name = Duron 650 | ||
| no image = Yes | | no image = Yes | ||
| Line 106: | Line 106: | ||
== Features == | == Features == | ||
| − | {{ | + | {{mpu features |
| em64t = | | em64t = | ||
| nx = | | nx = | ||
Revision as of 14:26, 13 December 2017
Template:mpu Duron 650 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2000. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 650 MHz with a bus capable of 200 MT/s with a TDP of 24.3 W.
Cache
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Halt State
- Sleep State
Documents
DataSheet
- AMD Duron Processor Model 3 Data Sheet; Publication # 23802; Rev: I; Issue Date: June 2001.
Other
- AMD Duron Processor Model 3 Revision Guide; Publication # 23865; Rev: K; Issue Date: October 2003.
Facts about "Duron 650 (Spitfire) - AMD"
| has feature | Halt State + and Sleep State + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |