Revision as of 21:50, 2 November 2017

Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY and introduced in early 2017. This chip, which operates at 1 GHz, incorporates 2,048 cores dissipating 180 W.

Overview

Introduced by PEZY along with their second-generation ZettaScaler-2.0 supercomputer series, the SC2 incorporates 2,048 cores along with 8-way SMT support for a total of 16,384 threads, twice as many cores as its predecessor.

Operating at 1 GHz, the PEZY-SC2 has a peak performance of 8.192 TFLOPS (single-precision) and 4.1 TFLOPS (double-precision) while consuming around 180 Watts. The PEZY-SC2 is designed using over 2.4 billion gates and is manufactured on TSMC's 16FF+ process.

In attempt to increase adaptability in the field of deep learning and AI as well as to increase throughput for specialized workloads, the PEZY-SC2 introduced support for 16-bit half precision floating point support. At 1 GHz, the SC2 can peak at 16.4 TFLOPS for half precision.

Cache

The SC2 a hexa-core MIPS P6600 process which has its own separate cache:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 6x64 KiB 4-way set associative   L1D$ 384 KiB 393,216 B 0.375 MiB 6x64 KiB 8-way set associative   L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB 8-way set associative

The SC2 integrates a multi-level cache hierarchy:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 12 MiB 12,288 KiB 12,582,912 B L1I$ 8 MiB 8,192 KiB 8,388,608 B per processor element   L1D$ 4 MiB 4,096 KiB 4,194,304 B 512x2 KiB per 2 processor elements   L2$ 12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB     per city   L3$ 40 MiB 40,960 KiB 41,943,040 B 0.0391 GiB     1x40 MiB shared LLC

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Memory Wide I/O Rate 2,000 MHz Width 1,024 bit Channels 4 Max Bandwidth 1.863 TiB/s 1,907.712 GiB/s 1,953,497.088 MiB/s 2,048.39 GB/s 2,048,390.163 MB/s 2.048 TB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 32 Configuration: 4x8