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Difference between revisions of "freescale/qoriq/p1010"
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'''QorIQ P1010''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 667 MHz and supports 32-bit DDR2/3 memory.
 
'''QorIQ P1010''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 667 MHz and supports 32-bit DDR2/3 memory.
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== Cache ==
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{{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}}
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{{cache size
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|l1 cache=64 KiB
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|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=32 KiB
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|l1d break=1x32 KiB
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|l1d desc=8-way set associative
 +
|l1d policy=
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|l2 cache=
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|l2 break=
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|l2 desc=
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|l2 policy=
 +
}}
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 +
== Memory controller ==
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{{memory controller
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|type=DDR3-800
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|ecc=Yes
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|controllers=1
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|channels=1
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|max bandwidth=2.98 GiB/s
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|bandwidth schan=2.98 GiB/s
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}}
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== Expansions ==
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* 2x 10/100/1000 Eithernet with SGMII
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* 2x PCIe 1.0a controllers with 2 SerDes
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* 2x USB 2.0
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* SD/MMC
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* SPI
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* 2x I2C
 +
* UART
 +
* SEC 3.1 Security Acceleration

Revision as of 22:31, 23 October 2017

Template:mpu QorIQ P1010 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 667 MHz and supports 32-bit DDR2/3 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Controllers1
Channels1
Max Bandwidth2.98 GiB/s
3,051.52 MiB/s
3.2 GB/s
3,199.751 MB/s
0.00291 TiB/s
0.0032 TB/s
Bandwidth
Single 2.98 GiB/s

Expansions

  • 2x 10/100/1000 Eithernet with SGMII
  • 2x PCIe 1.0a controllers with 2 SerDes
  • 2x USB 2.0
  • SD/MMC
  • SPI
  • 2x I2C
  • UART
  • SEC 3.1 Security Acceleration
Retrieved from "https://en.wikichip.org/w/index.php?title=freescale/qoriq/p1010&oldid=66177"
Facts about "QorIQ P1010 - Freescale"
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has ecc memory supporttrue +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description8-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
max memory bandwidth2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels1 +
supported memory typeDDR3-800 +