Semiconductor & Computer Engineering
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== Overview == | == Overview == | ||
| − | + | The chip has been designed by [[Qualcomm]] specifically for the data center. Specifically this architecture is an attempt to address high concurrency, high thread density while maintaining isolation and quality of service between the processes. The overall chip consists of 24 core duplexes incorporating 48 cores on a ring interconnect along with 6 channels of DDR4 and L3 cache distributed across the ring. The chip also integrates 32 PCIe 3.0 lanes, 8 SATA gen 3.0 lanes, and a mixture of various other I/O peripherals. | |
== System Architecture == | == System Architecture == | ||
Revision as of 16:04, 13 October 2017
| Edit Values | |
| Falkor µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Qualcomm |
| Manufacturer | TSMC |
| Introduction | 2017 |
| Process | 10 nm |
| Core Configs | 42 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 10-15 |
| Decode | 4-way |
| Instructions | |
| ISA | ARMv8 |
| Cache | |
| L1I Cache | 64 KiB/core 8-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
Falkor is an ARM microarchitecture designed by Qualcomm for the server market. Falkor-based microprocessors are manufactured on a 10 nm process and sold under the Centriq brand.
Contents
Process Technology
- Further information: 10 nm lithography process
Falkor-based chips are manufactured on TSMC's 10 nm process.
Architecture
Falkor is a new architecture designed by Qualcomm from the ground up for the server market. While some of the core architecture ressmbles Qualcomm's mobile cores, the overall system architecture is considerably different to anything Qualcomm has previously designed.
Overview
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This section is empty; you can help add the missing info by editing this page. |
Block Diagram
System Overview
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This section is empty; you can help add the missing info by editing this page. |
Individual Core
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This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
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This section is empty; you can help add the missing info by editing this page. |
Overview
The chip has been designed by Qualcomm specifically for the data center. Specifically this architecture is an attempt to address high concurrency, high thread density while maintaining isolation and quality of service between the processes. The overall chip consists of 24 core duplexes incorporating 48 cores on a ring interconnect along with 6 channels of DDR4 and L3 cache distributed across the ring. The chip also integrates 32 PCIe 3.0 lanes, 8 SATA gen 3.0 lanes, and a mixture of various other I/O peripherals.
System Architecture
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This section is empty; you can help add the missing info by editing this page. |
Core
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This section is empty; you can help add the missing info by editing this page. |
References
- Thomas Speier & Barry Wolford, "Qualcomm Centriq 2400 Processor." Hot Chips 29 Symposium (HCS), 2017 IEEE. IEEE, 2017.
- Barry Wolford, "Architecting a multi-core server SoC for the cloud", 2017 Linley Processor Conference
Documents
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This section is empty; you can help add the missing info by editing this page. |
| codename | Falkor + |
| core count | 42 + |
| designer | Qualcomm + |
| first launched | 2017 + |
| full page name | qualcomm/microarchitectures/falkor + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Falkor + |
| pipeline stages (max) | 15 + |
| pipeline stages (min) | 10 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |