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Difference between revisions of "socionext/sc2a11"
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'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.
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'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to 16 GiB of DDR4-2133 EEC memory.
  
 
== Cache ==
 
== Cache ==

Revision as of 09:22, 6 October 2017

Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to 16 GiB of DDR4-2133 EEC memory.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB2-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB4-way set associative 
L2$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  12x256 KiB16-way set associative 
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
     

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem12 GiB
Channels2
Max Bandwidth15.89 GiB/s
16,271.36 MiB/s
17.062 GB/s
17,061.758 MB/s
0.0155 TiB/s
0.0171 TB/s
Bandwidth
Single 15.89 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
PCIe
Revision2.0
Max Lanes4
UART
GP I/OYes


Graphics

This SoC has no integrated graphics processing unit.

Networking

  • 2x Gigabit Ethernet Interfaces

Storage

  • SPI
  • eMMC

Block diagram

SC2A11 block.png
Retrieved from "https://en.wikichip.org/w/index.php?title=socionext/sc2a11&oldid=65609"
Facts about "SC2A11 - Socionext"
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SC2A11 - Socionext#io +
has ecc memory supporttrue +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description4-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description2-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
max memory bandwidth15.89 GiB/s (16,271.36 MiB/s, 17.062 GB/s, 17,061.758 MB/s, 0.0155 TiB/s, 0.0171 TB/s) +
max memory channels2 +
max pcie lanes4 +
supported memory typeDDR4-2133 +