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Difference between revisions of "hisilicon/k3/k3v2"
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'''K3V2''' is a {{arch|32}} [[quad-core]] mobile [[ARM]] microprocessor introduced by [[HiSilicon]] in early [[2012]]. This chip, which is fabricated on a [[40 nm process]], incorporates four {{armh|Cortex-A9|l=arch}} cores operating at 1.2 GHz. The K3V2 integrated [[Vivante]]'s {{vivante|GC4000}} (16 cores) [[IGP]] and supports up to 2 channels of LPDDR2-900 memory.
 
'''K3V2''' is a {{arch|32}} [[quad-core]] mobile [[ARM]] microprocessor introduced by [[HiSilicon]] in early [[2012]]. This chip, which is fabricated on a [[40 nm process]], incorporates four {{armh|Cortex-A9|l=arch}} cores operating at 1.2 GHz. The K3V2 integrated [[Vivante]]'s {{vivante|GC4000}} (16 cores) [[IGP]] and supports up to 2 channels of LPDDR2-900 memory.
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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{{cache size
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|l1 cache=256 KiB
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|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
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|l1i desc=4-way set associative
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|l1d cache=128 KiB
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|l1d break=4x32 KiB
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|l1d desc=4-way set associative
 +
|l2 cache=1 MiB
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|l2 break=1x1 MiB
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|l2 desc=8-way set associative
 +
}}

Revision as of 04:14, 6 September 2017

Template:mpu K3V2 is a 32-bit quad-core mobile ARM microprocessor introduced by HiSilicon in early 2012. This chip, which is fabricated on a 40 nm process, incorporates four Cortex-A9 cores operating at 1.2 GHz. The K3V2 integrated Vivante's GC4000 (16 cores) IGP and supports up to 2 channels of LPDDR2-900 memory.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB8-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/k3/k3v2&oldid=63630"
Facts about "K3V2 - HiSilicon"
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l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description4-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +