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Difference between revisions of "intel/xeon w/w-2175"
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'''W-2175''' is a {{arch|64}} [[14-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at ? GHz with a [[TDP]] of 140 W and a {{intel|turbo boost}} frequency of up to ? GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory. | '''W-2175''' is a {{arch|64}} [[14-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at ? GHz with a [[TDP]] of 140 W and a {{intel|turbo boost}} frequency of up to ? GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=896 KiB | ||
+ | |l1i cache=448 KiB | ||
+ | |l1i break=14x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=448 KiB | ||
+ | |l1d break=14x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=14 MiB | ||
+ | |l2 break=14x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=19.25 MiB | ||
+ | |l3 break=14x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} |
Revision as of 10:15, 31 August 2017
Template:mpu W-2175 is a 64-bit 14-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at ? GHz with a TDP of 140 W and a turbo boost frequency of up to ? GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon W-2175 - Intel"
l1$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) + |