From WikiChip
Difference between revisions of "intel/xeon w/w-2195"
Line 37: | Line 37: | ||
}} | }} | ||
'''W-2195''' is a {{arch|64}} [[18-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 2.3 GHz with a [[TDP]] of 140 W and a {{intel|turbo boost}} frequency of up to 4.3 GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory. | '''W-2195''' is a {{arch|64}} [[18-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 2.3 GHz with a [[TDP]] of 140 W and a {{intel|turbo boost}} frequency of up to 4.3 GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory. | ||
+ | |||
+ | {{unknown features}} | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1.125 MiB | ||
+ | |l1i cache=576 KiB | ||
+ | |l1i break=18x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=576 KiB | ||
+ | |l1d break=18x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=18 MiB | ||
+ | |l2 break=18x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=24.75 MiB | ||
+ | |l3 break=18x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} |
Revision as of 10:15, 31 August 2017
Template:mpu W-2195 is a 64-bit 18-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 2.3 GHz with a TDP of 140 W and a turbo boost frequency of up to 4.3 GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Facts about "Xeon W-2195 - Intel"
l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |