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Difference between revisions of "intel/celeron/807ue"
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== Cache == | == Cache == | ||
+ | {{main|intel/microarchitectures/sandy_bridge#Memory_Hierarchy|l1=Sandy Bridge § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=64 KiB | ||
+ | |l1i cache=32 KiB | ||
+ | |l1i break=1x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=32 KiB | ||
+ | |l1d break=1x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=256 KiB | ||
+ | |l2 break=1x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=1.5 MiB | ||
+ | |l3 break=1x1.5 MiB | ||
+ | |l3 desc=12-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
== Memory controller == | == Memory controller == |
Revision as of 21:58, 19 August 2017
Cache
- Main article: Sandy Bridge § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Graphics
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Celeron 807UE - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 807UE - Intel#pcie + |
has ecc memory support | true + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
max memory bandwidth | 9.93 GiB/s (10,168.32 MiB/s, 10.662 GB/s, 10,662.256 MB/s, 0.0097 TiB/s, 0.0107 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR3-1333 + and DDR3-1066 + |