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Difference between revisions of "intel/atom/c3308"
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Revision as of 23:03, 16 August 2017
Template:mpu Atom C3308 is a 64-bit dual-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3308, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 1.6 GHz with a TDP of 9.5 W and a turbo boost frequency of up to 2.1 GHz. The C3308 supports up to a single channel of 128 GiB of DDR4-1866 ECC memory. This model is part of Denverton's Internet of Things and eTEMP SKUs which come with integrated QuickAssist Technology and support extended ambient operating temperature (-40 °C to 85 °C).
Contents
Cache
- Main article: Goldmont § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Atom C3308 - Intel"
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Memory Protection Extensions + |
has intel enhanced speedstep technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 112 KiB (114,688 B, 0.109 MiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 48 KiB (49,152 B, 0.0469 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
max memory bandwidth | 13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) + |
max memory channels | 1 + |
part of | Internet of Things and eTEMP SKUs + |
supported memory type | DDR3L-1600 + and DDR4-1866 + |
x86/has memory protection extensions | true + |