Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon gold/5122"
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|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Revision as of 15:29, 13 December 2017
| Edit Values | |
| Xeon Gold 5122 | |
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| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 5122 |
| Part Number | BX806735122, CD8067303330702 |
| S-Spec | SR3AT QMRN (QS) |
| Market | Server |
| Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
| Release Price | $1221.00 |
| Shop | Amazon |
| General Specs | |
| Family | Xeon Gold |
| Series | 5000 |
| Locked | Yes |
| Frequency | 3,600 MHz |
| Turbo Frequency | 3,700 MHz (1 core) |
| Clock multiplier | 36 |
| CPUID | 0x50654 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Skylake (server) |
| Platform | Purley |
| Chipset | Lewisburg |
| Core Name | Skylake SP |
| Core Family | 6 |
| Core Stepping | H0 |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 8 |
| Max Memory | 768 GiB |
| Multiprocessing | |
| Max SMP | 4-Way (Multiprocessor) |
| Electrical | |
| TDP | 105 W |
| Tcase | 0 °C – 71 °C |
| TDTS | 0 °C – 104 °C |
| Packaging | |
| Template:packages/intel/fclga-3647 | |
Xeon Gold 5122 is a 64-bit quad-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5122, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.6 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache
- Main article: Skylake § Cache
The Xeon Gold 5122 features a considerably larger non-default 16.5 MiB of L3, a size that would normally be found on a 12-core part.
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
Frequencies
- See also: Intel's CPU Frequency Behavior
| Mode | Base | Turbo Frequency/Active Cores | |||
|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | ||
| Normal | 3,600 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz |
| AVX2 | 3,300 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz |
| AVX512 | 2,700 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz |
Facts about "Xeon Gold 5122 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5122 - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
| has intel enhanced speedstep technology | true + |
| has intel speed shift technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + |
| max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
| max memory channels | 6 + |
| max pcie lanes | 48 + |
| supported memory type | DDR4-2400 + |