Latest revision as of 15:32, 13 December 2017

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R-Car E1
General Info
Designer	Renesas, ARM Holdings
Manufacturer	TSMC
Model Number	E1
Part Number	μPD35004
Market	Embedded
Introduction	August 25, 2011 (announced) June, 2012 (launched)
Release Price	$30
General Specs
Family	R-Car
Series	1st Gen
Frequency	533 MHz
Microarchitecture
ISA	ARMv7 (ARM)
Microarchitecture	Cortex-A9
Core Name	Cortex-A9
Process	40 nm
Technology	CMOS
Word Size	32 bit
Cores	1
Threads	1
Max Memory	1 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.1 V
VI/O	3.3 V
Packaging
Package FCBGA-429 (BGA) Dimension 18 mm x 18 mm Pitch 0.80 mm Ball Count 429 Interconnect BGA-429

R-Car E1 is an entry-level performance embedded SoC for the automotive industry designed by Renesas and introduced in 2011. The E1 features a single Cortex-A9 core operating at 533 MHz. This chip incorporates Imagination's PowerVR SGX531 GPU operating at 177 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.

Announced in mid-2011, Renesas expected the E1 to begin mass production in June 2012 and reach a rate of 100,000 units per month in June 2013.

Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 64 KiB 65,536 B 0.0625 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 4-way set associative   L1D$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 4-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066, DDR2-533 Supports ECC No Max Mem 1 GiB Controllers 1 Channels 1 Width 32 bit Max Bandwidth 1.99 GiB/s 2,037.76 MiB/s 2.137 GB/s 2,136.746 MB/s 0.00194 TiB/s 0.00214 TB/s Bandwidth Single 1.99 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
	USB Revision 2.0 Ports 2 Rate 480 Mbps UART Ports 8 SATA Revision 3.0 Ports 1 I²C Ports 4 GP I/O Yes JTAG Yes

• MLB (MOST150) 6-Pin I/F
• 2 x CAN 32 Message Buffers
• MMC
• 3 x SD

Graphics[edit]

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX531 Designer Imagination Technologies Execution Units 1 Max Displays 2 Frequency 177 MHz 0.177 GHz 177,000 KHz Standards OpenGL ES 2.0

Features[edit]

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv3 Vector Floating Point (VFP) v3 Extension NEON Advanced SIMD extension Jazelle Direct Bytecode eXecution

Block Diagram[edit]