Semiconductor & Computer Engineering
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:: Yea my mistake, I reverted it. I was going through new 14/7nm process info and mixed up some stuff. My bad. --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 18:01, 20 July 2017 (EDT) | :: Yea my mistake, I reverted it. I was going through new 14/7nm process info and mixed up some stuff. My bad. --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 18:01, 20 July 2017 (EDT) | ||
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| + | == Intel SoC diagrams == | ||
| + | Hey, can you switch the Intel diagrams to correctly correspond to how the cache layout changes in Skylake & Kaby? As they shifted to the sides.--[[User:David|David]] ([[User talk:David|talk]]) 23:24, 7 September 2017 (EDT) | ||
Revision as of 22:24, 7 September 2017
Goldmont
?> Hello World! <?
Re "Goldmont" article. You stuffed all my edits under "latency", even though most of them are about throughput. Throughput != latency. — Preceding unsigned comment added by 213.175.37.10 (talk • contribs)
- Yup my bad. It should've been throughput. I've changed it accordingly. --At32Hz (talk) 09:51, 27 October 2016 (EDT)
14 nm
"14nm lithography article" You reverted my edit about the sram density, while the Intel slide in the article clearly states that the sram density is higher than that of a logic tall cell. So do you claim the slide is wrong, or do i miss something obvious? — Preceding unsigned comment added by Nible (talk • contribs) 09:20, Jun 17, 2005 (UTC)
- Yea my mistake, I reverted it. I was going through new 14/7nm process info and mixed up some stuff. My bad. --At32Hz (talk) 18:01, 20 July 2017 (EDT)
Intel SoC diagrams
Hey, can you switch the Intel diagrams to correctly correspond to how the cache layout changes in Skylake & Kaby? As they shifted to the sides.--David (talk) 23:24, 7 September 2017 (EDT)