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Difference between revisions of "intel/xeon platinum/8160m"
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'''Xeon Platinum 8160M''' is a {{arch|64}} [[24-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8160M, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory. | '''Xeon Platinum 8160M''' is a {{arch|64}} [[24-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8160M, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory. | ||
− | == | + | == Cache == |
− | {{ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
− | | | + | {{cache size |
− | | | + | |l1 cache=1.5 MiB |
− | + | |l1i cache=768 KiB | |
− | + | |l1i break=24x32 KiB | |
− | + | |l1i desc=8-way set associative | |
− | + | |l1d cache=768 KiB | |
− | + | |l1d break=24x32 KiB | |
− | + | |l1d desc=8-way set associative | |
− | + | |l1d policy=write-back | |
− | + | |l2 cache=24 MiB | |
− | + | |l2 break=24x1 MiB | |
− | + | |l2 desc=16-way set associative | |
− | + | |l2 policy=write-back | |
− | + | |l3 cache=33 MiB | |
− | + | |l3 break=24x1.375 MiB | |
− | + | |l3 desc=11-way set associative | |
− | + | |l3 policy=write-back | |
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Revision as of 04:14, 12 July 2017
Template:mpu Xeon Platinum 8160M is a 64-bit 24-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8160M, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Platinum 8160M - Intel"
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) + |