From WikiChip
Difference between revisions of "intel/xeon platinum/8180"
< intel‎ | xeon platinum

Line 58: Line 58:
 
|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
}}
 
 
== Memory controller ==
 
{{memory controller
 
|type=DDR4-2666
 
|ecc=Yes
 
|max mem=
 
|controllers=1
 
|channels=6
 
|max bandwidth=119.21 GiB/s
 
|bandwidth schan=19.89 GiB/s
 
|bandwidth dchan=39.72 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 
|bandwidth hchan=119.21 GiB/s
 
}}
 
 
== Features ==
 
{{x86 features
 
|real=Yes
 
|protected=Yes
 
|smm=Yes
 
|fpu=Yes
 
|x8616=Yes
 
|x8632=Yes
 
|x8664=Yes
 
|nx=Yes
 
|mmx=Yes
 
|emmx=Yes
 
|sse=Yes
 
|sse2=Yes
 
|sse3=Yes
 
|ssse3=Yes
 
|sse41=Yes
 
|sse42=Yes
 
|sse4a=No
 
|avx=Yes
 
|avx2=Yes
 
 
|abm=Yes
 
|tbm=No
 
|bmi1=Yes
 
|bmi2=Yes
 
|fma3=Yes
 
|fma4=No
 
|aes=Yes
 
|rdrand=Yes
 
|sha=No
 
|xop=No
 
|adx=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt2=No
 
|tbmt3=No
 
|bpt=No
 
|eist=Yes
 
|sst=No
 
|flex=No
 
|fastmem=No
 
|isrt=No
 
|sba=No
 
|mwt=No
 
|sipp=No
 
|att=No
 
|ipt=No
 
|tsx=Yes
 
|txt=No
 
|ht=Yes
 
|vpro=Yes
 
|vtx=Yes
 
|vtd=Yes
 
|ept=Yes
 
|mpx=Yes
 
|sgx=No
 
|securekey=No
 
|osguard=Yes
 
|3dnow=No
 
|e3dnow=No
 
|smartmp=No
 
|powernow=No
 
|amdvi=No
 
|amdv=No
 
|rvi=No
 
|smt=No
 
|sensemi=No
 
|xfr=No
 
 
}}
 
}}

Revision as of 03:16, 12 July 2017

Template:mpu Xeon Platinum 8180 is a 64-bit 28-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8180, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.5 GHz with a TDP of 205 W and a turbo boost frequency of up to 3.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.75 MiB
1,792 KiB
1,835,008 B
L1I$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associative 
L1D$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associativewrite-back

L2$28 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
  28x1 MiB16-way set associativewrite-back

L3$38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
  28x1.375 MiB11-way set associativewrite-back
l1$ size1,792 KiB (1,835,008 B, 1.75 MiB) +
l1d$ description8-way set associative +
l1d$ size896 KiB (917,504 B, 0.875 MiB) +
l1i$ description8-way set associative +
l1i$ size896 KiB (917,504 B, 0.875 MiB) +
l2$ description16-way set associative +
l2$ size28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) +
l3$ description11-way set associative +
l3$ size38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) +