From WikiChip
Difference between revisions of "intel/xeon gold/5120"
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|l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2400 | ||
+ | |ecc=Yes | ||
+ | |max mem=768 GiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=107.3 GiB/s | ||
+ | |bandwidth schan=17.88 GiB/s | ||
+ | |bandwidth dchan=35.76 GiB/s | ||
+ | |bandwidth qchan=71.53 GiB/s | ||
+ | |bandwidth hchan=107.3 GiB/s | ||
}} | }} |
Revision as of 20:53, 11 July 2017
Template:mpu Xeon Gold 5120 is a 64-bit tetradeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5120, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.2 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Xeon Gold 5120 - Intel"
has ecc memory support | true + |
l1$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
supported memory type | DDR4-2400 + |