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Difference between revisions of "intel/xeon silver/4112"
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|bandwidth qchan=71.53 GiB/s
 
|bandwidth qchan=71.53 GiB/s
 
|bandwidth hchan=107.3 GiB/s
 
|bandwidth hchan=107.3 GiB/s
 +
}}
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== Expansions ==
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{{expansions
 +
| pcie revision      = 3.0
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| pcie lanes        = 48
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| pcie config        = x16
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| pcie config 2      = x8
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| pcie config 2      = x4
 
}}
 
}}

Revision as of 17:11, 11 July 2017

Template:mpu Xeon Silver 4112 is a 64-bit quad-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4112, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x1 MiB16-way set associativewrite-back
L3$5.5 MiB
5,632 KiB
5,767,168 B
0.00537 GiB
  4x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x4
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_silver/4112&oldid=54273"
Facts about "Xeon Silver 4112 - Intel"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel + and Xeon Silver 4112 - Intel#io +
base frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +
chipsetLewisburg +
clock multiplier26 +
core count4 +
core family6 +
core nameSkylake SP +
core steppingU0 +
cpuid0x50654 +
designerIntel +
familyXeon Silver +
first announcedJuly 11, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon silver/4112 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Transactional Synchronization Extensions +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description11-way set associative +
l3$ size8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature349.15 K (76 °C, 168.8 °F, 628.47 °R) +
max cpu count2 +
max dts temperature89 °C +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number4112 +
nameXeon Silver 4112 +
packageFCLGA-3647 +
part numberBX806734112 + and CD8067303562100 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 473.00 (€ 425.70, £ 383.13, ¥ 48,875.09) +
s-specSR3GN +
s-spec (qs)QN0E +
series4000 +
smp interconnectUPI +
smp interconnect links2 +
smp interconnect rate9.6 GT/s +
smp max ways2 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2400 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count8 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +