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Difference between revisions of "intel/celeron/3955u"
< intel‎ | celeron

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== Graphics ==
 
== Graphics ==
−
{{integrated graphic
+
{{integrated graphics
−
| gpu               = Intel HD Graphics 510
+
| gpu                 = HD Graphics 510
−
| displays           = 3
+
| device id          = 0x1906
−
| frequency         = 300 MHz
+
| designer            = Intel
−
| max frequency     = 900 MHz
+
| execution units    = 12
−
| max memory         = 1700 MiB
+
| max displays       = 3
−
| output edp         = Yes
+
| max memory          = 32 GiB
−
| output dp         = Yes
+
| frequency           = 300 MHz
−
| output hdmi       = Yes
+
| max frequency       = 900 MHz
−
| output vga         =  
+
 
−
| output dvi         = Yes
+
| output crt          =
 +
| output sdvo         =  
 +
| output dsi          =
 +
| output edp         = Yes
 +
| output dp           = Yes
 +
| output hdmi         = Yes
 +
| output vga         =  
 +
| output dvi         = Yes
 +
 
 
| directx ver        = 12
 
| directx ver        = 12
 
| opengl ver        = 4.4
 
| opengl ver        = 4.4
 +
| opencl ver        = 2.0
 +
| hdmi ver          = 1.4a
 +
| dp ver            = 1.2
 +
| edp ver            = 1.3
 
| max res hdmi      = 4096x2304
 
| max res hdmi      = 4096x2304
 
| max res hdmi freq  = 24 Hz
 
| max res hdmi freq  = 24 Hz
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| max res vga        =  
 
| max res vga        =  
 
| max res vga freq  =  
 
| max res vga freq  =  
 +
 +
| features            = Yes
 +
| intel quick sync    = Yes
 +
| intel intru 3d      =
 +
| intel insider        =
 +
| intel widi          =
 +
| intel fdi            =
 +
| intel clear video    =
 +
| intel clear video hd = Yes
 
}}
 
}}
 +
{{skylake hardware accelerated video table|col=1}}
  
 
== Features ==
 
== Features ==

Revision as of 20:12, 3 July 2017

Template:mpu Celeron 3955U is a 64-bit dual-core budget x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2 GHz. The 3955U has a TDP of 15 W with a configurable-down TDP of 10 W. This chip incorporates the HD Graphics 510 GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB write-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133, LPDDR3-1866, DDR3L-1600
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 510
DesignerIntelDevice ID0x1906
Execution Units12Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel Clear Video HD

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/3955u&oldid=50223"
Facts about "Celeron 3955U - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron 3955U - Intel#io +
device id0x1906 +
has ecc memory supportfalse +
integrated gpuHD Graphics 510 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes12 +
supported memory typeDDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 +