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Difference between revisions of "vti/vl86cx/vy86c810"
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| + | '''VY86C810''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1996]]. This processor is based on the {{armh|ARM7|l=arch}} microarchitecture ({{armh|ARM710|l=core}} core) and is manufactured on [[VLSI Technology|VLSI]]'s [[0.5 µm process]] and operating at 50 MHz. | ||
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| + | == Cache == | ||
| + | {{main|arm_holdings/microarchitectures/arm8#Memory_Hierarchy|l1=ARM8 § Cache}} | ||
| + | {{cache size | ||
| + | |l1 cache=8 KiB | ||
| + | |l1 break=1x8 KiB | ||
| + | |l1 desc=64-way set associative | ||
| + | |l1 policy=write-through | ||
}} | }} | ||
Revision as of 18:22, 1 July 2017
Template:mpu VY86C810 is a 32-bit ARM microprocessor designed by ARM and introduce by VTI in 1996. This processor is based on the ARM7 microarchitecture (ARM710 core) and is manufactured on VLSI's 0.5 µm process and operating at 50 MHz.
Cache
- Main article: ARM8 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "VY86C810 - VTI"
| l1$ description | 64-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |