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Difference between revisions of "intrinsity/fastmath/fastmath-3"
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| name = FastMATH 3 GHz | | name = FastMATH 3 GHz | ||
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Latest revision as of 15:31, 13 December 2017
Edit Values | |
FastMATH 3 GHz | |
General Info | |
Designer | Intrinsity |
Manufacturer | TSMC |
Model Number | FastMATH-3 |
Market | Embedded |
Introduction | 2003 (announced) |
General Specs | |
Family | FastMATH |
Frequency | 3,000 MHz |
Bus type | RapidIO |
Bus speed | 500 MHz |
Bus rate | 4 GT/s |
Microarchitecture | |
Microarchitecture | FashMATH |
Process | 130 nm |
Technology | Dynamic CMOS |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 1 GiB |
Electrical | |
Vcore | 1.25 V |
The FastMATH 3 GHz was a microprocessor developed by Intrinsity operating at 3 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit.
Cache[edit]
- Main article: FastMATH § Cache
Cache Info [Edit Values] | ||
L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block |
L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode |
L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments) |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR-400 |
Controllers | 1 |
Channels | 2 |
Max memory | 1 GB |
Matrix and Vector Unit[edit]
- SIMD architecture
- Operates on 4x4 array of 32-bit elements
- Fixed-point matrix, vector, and scalar data types
Features[edit]
- JTAG interface
- 8-bit or 32-bit wide bus operates up to 66 MHz
Facts about "FastMATH 3 GHz - Intrinsity"
has feature | JTAG + |
l1d$ description | 256 blocks × 16 words/block + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 256 blocks × 16 words/block + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |