Semiconductor & Computer Engineering
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== Release Dates == | == Release Dates == | ||
| − | + | DEC first announced their 21064 architecture in February of [[1992]]. Alpha 21064-based chips were first introduced during [[COMDEX]] on November 20, 1992. | |
== Process Technology == | == Process Technology == | ||
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== Architecture == | == Architecture == | ||
{{empty section}} | {{empty section}} | ||
| + | |||
| + | == Die == | ||
| + | * [[0.75 µm process]] | ||
| + | * 3 metal layers | ||
| + | * 1,680,000 transistors | ||
| + | * 14 mm x 17 mm | ||
| + | * 238 mm² die size | ||
== References == | == References == | ||
* McLellan, Edward. "The Alpha AXP architecture and 21064 processor." IEEE Micro 13.3 (1993): 36-47. | * McLellan, Edward. "The Alpha AXP architecture and 21064 processor." IEEE Micro 13.3 (1993): 36-47. | ||
Revision as of 15:35, 16 June 2017
| Edit Values | |
| Alpha 21064 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC |
| Manufacturer | DEC |
| Introduction | November 20 1992 |
| Process | 0.75 µm, 0.675 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Superscalar |
| OoOE | No |
| Speculative | Yes |
| Reg Renaming | No |
| Stages | 7-12 |
| Decode | 2-way |
| Instructions | |
| ISA | Alpha |
| Cache | |
| L1I Cache | 8 KiB/core direct-mapped |
| L1D Cache | 8 KiB/core direct-mapped |
| L2 Cache | 0.125-16 MiB/motherboard |
| Succession | |
Alpha 21064 was the first Alpha microarchitecture designed by DEC and introduced in 1992.
Contents
Etymology
The microarchitecture name Alpha 21064 is composed of both the ISA and the implementation. In particular, the "Alpha" refers to DEC's Alpha AXP instruction set architecture while the "21064" refers to a "21st century"-ready 64-bit "0th generation" microarchitecture.
Release Dates
DEC first announced their 21064 architecture in February of 1992. Alpha 21064-based chips were first introduced during COMDEX on November 20, 1992.
Process Technology
- See also: 0.75 µm process
Alpha 21064 was manufactured on DEC's CMOS-4, their then-newest 0.75 µm process. The process offered three levels of aluminum interconnects and a nominal 3.3 V power supply. Note that prior to the introduction of the 21064, DEC produced early "assistance" samples for software developers which were manufactured on an older CMOS-3 process (1 µm). For that reason those chips also had reduced cache amount, in addition to no FPU support.
Compatibility
| Vendor | OS | Version | Notes |
|---|---|---|---|
| Microsoft | Windows | Windows NT | Support |
| DEC | OpenVMS | OpenVMS AXP V1.0 | Initial OpenVMS support |
| DEC | OSF/1 AXP | 1.0 | |
| Novell | Netware | 3.2 |
Architecture
 |
This section is empty; you can help add the missing info by editing this page. |
Die
- 0.75 µm process
- 3 metal layers
- 1,680,000 transistors
- 14 mm x 17 mm
- 238 mm² die size
References
- McLellan, Edward. "The Alpha AXP architecture and 21064 processor." IEEE Micro 13.3 (1993): 36-47.
| codename | Alpha 21064 + |
| core count | 1 + |
| designer | DEC + |
| first launched | November 20, 1992 + |
| full page name | dec/microarchitectures/alpha 21064 + |
| instance of | microarchitecture + |
| instruction set architecture | Alpha + |
| manufacturer | DEC + |
| microarchitecture type | CPU + |
| name | Alpha 21064 + |
| pipeline stages (max) | 12 + |
| pipeline stages (min) | 7 + |
| process | 750 nm (0.75 μm, 7.5e-4 mm) + and 675 nm (0.675 μm, 6.75e-4 mm) + |