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(Created page with "{{dec title|Process Technology}} This article details details '''DEC's Semiconductor Process Technology''' history for research and posterity. The table below shows t...") |
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The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist. | The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist. | ||
| + | |||
| + | == Timeline == | ||
| + | <div style="overflow-x: auto;" class="scrollable"> | ||
| + | <table class="wikitable" style="text-align: center;"> | ||
| + | <tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th colspan="4">Attributes</th></tr> | ||
| + | {{dec proc tech |year= |name=ZMOS |mlayers=2 |node=3 µm | ||
| + | |archs=V-11, MicroVAX II | ||
| + | |a1=T<sub>ox</sub> |d1=43 nm | ||
| + | }} | ||
| + | {{dec proc tech |year= |name=CMOS-1 |mlayers= |node=2 µm | ||
| + | |archs= | ||
| + | |a1=T<sub>ox</sub> |d1= | ||
| + | }} | ||
| + | {{dec proc tech |year= |name=CMOS-2 |mlayers= |node=1.5 µm | ||
| + | |archs= | ||
| + | |a1=T<sub>ox</sub> |d1= | ||
| + | }} | ||
| + | {{dec proc tech |year= |name=CMOS-3 |mlayers= |node=1 µm | ||
| + | |archs= | ||
| + | |a1=T<sub>ox</sub> |d1= | ||
| + | }} | ||
| + | {{dec proc tech |year=1991 |name=CMOS-4 |mlayers=3 |node=0.75 µm | ||
| + | |archs=NVAX, Alpha 21064 | ||
| + | |a1=T<sub>ox</sub> |d1=10.5 nm | ||
| + | |a2=V<sub>dd</sub> |d2=3.3 V |a22=SRAM |d22= 100 µm² | ||
| + | |a3=L<sub>g</sub> |d3=0.75 µm |a32=L<sub>eff</sub> |d32=0.50 µm | ||
| + | }} | ||
| + | {{dec proc tech |year= |name=CMOS-4S |mlayers=3 |node=0.675 µm | ||
| + | |archs= | ||
| + | |a1=T<sub>ox</sub> |d1= | ||
| + | }} | ||
| + | {{dec proc tech |year=1994 |name=CMOS-5 |mlayers=4 |node=0.5 µm | ||
| + | |archs= | ||
| + | |a1=T<sub>ox</sub> |d1= | ||
| + | }} | ||
| + | {{dec proc tech |year= |name=CMOS-6 |mlayers=4 |node=0.35 µm | ||
| + | |archs= | ||
| + | |a1=T<sub>ox</sub> |d1= | ||
| + | }} | ||
| + | {{dec proc tech |year=1997 |name=CMOS-7 |mlayers= |node=0.25 µm | ||
| + | |archs= | ||
| + | |a1=T<sub>ox</sub> |d1= | ||
| + | }} | ||
| + | <tr><td>1997</td><td colspan="8">Fab-6 in Hudson, Mass was sold to [[Intel]] which consequently upgraded it for $800M to Intel's propiatery [[0.18 µm]] (see {{intel|Process|Intel's Process}}).</td></tr> | ||
| + | <tr><td>2013</td><td colspan="8">In late 2013 Intel announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology.</td></tr> | ||
| + | </table> | ||
| + | </div> | ||
| + | |||
| + | <!-- | ||
| + | |a12=Gate Dielectric |d12=SiO<sub>2</sub> | ||
| + | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22= 1120 µm² | ||
| + | |a3=L<sub>g</sub> |d3=3.0 µm | ||
| + | |a4=CPP |d4=7 µm |a42=MMP |d42= | ||
| + | --> | ||
Revision as of 16:56, 11 June 2017
This article details details DEC's Semiconductor Process Technology history for research and posterity.
The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist.
Timeline
| Year | Process | Node | MLayers | µarchs | Attributes | |||
|---|---|---|---|---|---|---|---|---|
| ZMOS | 3 µm | 2 | V-11, MicroVAX II | Tox | 43 nm | |||
| CMOS-1 | 2 µm | Tox | ||||||
| CMOS-2 | 1.5 µm | Tox | ||||||
| CMOS-3 | 1 µm | Tox | ||||||
| 1991 | CMOS-4 | 0.75 µm | 3 | NVAX, Alpha 21064 | Tox | 10.5 nm | ||
| Vdd | 3.3 V | SRAM | 100 µm² | |||||
| Lg | 0.75 µm | Leff | 0.50 µm | |||||
| CMOS-4S | 0.675 µm | 3 | Tox | |||||
| 1994 | CMOS-5 | 0.5 µm | 4 | Tox | ||||
| CMOS-6 | 0.35 µm | 4 | Tox | |||||
| 1997 | CMOS-7 | 0.25 µm | Tox | |||||
| 1997 | Fab-6 in Hudson, Mass was sold to Intel which consequently upgraded it for $800M to Intel's propiatery 0.18 µm (see Intel's Process). | |||||||
| 2013 | In late 2013 Intel announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology. | |||||||