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Difference between revisions of "amd/cores/rome"
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| + | '''Rome''' is the codename for [[AMD]]'s highest-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 2|l=arch}} microarchitecture. Rome-based chips are set to be fabricated on GlobalFoundries' [[7 nm process]]. | ||
Revision as of 18:30, 16 May 2017
| Edit Values | |
| Rome | |
 | |
| General Info | |
| Designer | AMD |
| Manufacturer | GlobalFoundries |
| Introduction | May 16, 2017 (announced) |
| Microarchitecture | |
| ISA | x86-64 |
| Microarchitecture | Zen 2 |
| Word Size | 8 octets 64 bit16 nibbles |
| Process | 7 nm 0.007 μm 7.0e-6 mm |
| Technology | CMOS |
| Succession | |
Rome is the codename for AMD's highest-performance enterprise-level server multiprocessors based on the Zen 2 microarchitecture. Rome-based chips are set to be fabricated on GlobalFoundries' 7 nm process.
Facts about "Rome - Cores - AMD"
| back image | .jpg) + |
| designer | AMD + |
| first announced | May 16, 2017 + |
| first launched | August 7, 2019 + |
| instance of | core + |
| isa | x86-64 + |
| isa family | x86 + |
| main image | .jpg) + |
| main image caption | Package front + |
| manufacturer | TSMC + and GlobalFoundries + |
| microarchitecture | Zen 2 + |
| name | Rome + |
| package | FCLGA-4094 + and SP3 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
| socket | LGA-4094 + and SP3 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |
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