From WikiChip
Difference between revisions of "intel/xeon gold/6140"
Line 59: | Line 59: | ||
| die length = | | die length = | ||
| word size = 64 bit | | word size = 64 bit | ||
− | | core count = | + | | core count = 18 |
− | | thread count = | + | | thread count = 36 |
− | | max cpus = | + | | max cpus = 2 |
| max memory = | | max memory = | ||
Line 108: | Line 108: | ||
| socket 0 type = LGA | | socket 0 type = LGA | ||
}} | }} | ||
− | '''Xeon Gold 6140''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6140 operates at 2.3 GHz | + | '''Xeon Gold 6140''' is a {{arch|64}} [[x86]] high-performance server [[octadeca-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6140 operates at 2.3 GHz. |
{{unknown features}} | {{unknown features}} | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1.125 MiB | ||
+ | |l1i cache=576 KiB | ||
+ | |l1i break=18x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=576 KiB | ||
+ | |l1d break=18x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=18 MiB | ||
+ | |l2 break=18x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=24.75 MiB | ||
+ | |l3 break=18x1.375 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem= | ||
+ | |controllers=1 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.89 GiB/s | ||
+ | |bandwidth dchan=39.72 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} |
Revision as of 12:54, 26 May 2017
Template:mpu Xeon Gold 6140 is a 64-bit x86 high-performance server octadeca-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6140 operates at 2.3 GHz.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||
|
Facts about "Xeon Gold 6140 - Intel"
has ecc memory support | true + |
l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
supported memory type | DDR4-2666 + |