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    Difference between revisions of "intel/xeon gold/6142m"    
                	
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{{intel title|Xeon Gold 6142M}}  | {{intel title|Xeon Gold 6142M}}  | ||
| + | {{mpu  | ||
| + | | future              = Yes  | ||
| + | | name                = Xeon Gold 6142M  | ||
| + | | no image            = Yes  | ||
| + | | image               =   | ||
| + | | image size          =   | ||
| + | | caption             =   | ||
| + | | designer            = Intel  | ||
| + | | manufacturer        = Intel  | ||
| + | | model number        = 6142M  | ||
| + | | part number         = CD8067303405700  | ||
| + | | part number 1       =   | ||
| + | | part number 2       =   | ||
| + | | s-spec              = SR3B1  | ||
| + | | s-spec 2            =   | ||
| + | | market              = Server  | ||
| + | | first announced     = April 25, 2017  | ||
| + | | first launched      =   | ||
| + | | last order          =   | ||
| + | | last shipment       =   | ||
| + | | release price       =   | ||
| + | |||
| + | | family              = Xeon Gold  | ||
| + | | series              = 6100  | ||
| + | | locked              = Yes  | ||
| + | | frequency           = 2.6 GHz  | ||
| + | | turbo frequency     =   | ||
| + | | turbo frequency1    =   | ||
| + | | turbo frequency2    =   | ||
| + | | turbo frequency3    =   | ||
| + | | turbo frequency4    =   | ||
| + | | turbo frequency5    =   | ||
| + | | turbo frequency6    =   | ||
| + | | turbo frequency7    =   | ||
| + | | turbo frequency8    =   | ||
| + | | bus type            = DMI 3.0  | ||
| + | | bus speed           =   | ||
| + | | bus rate            = 8 GT/s  | ||
| + | | bus links           = 4  | ||
| + | | clock multiplier    = 26  | ||
| + | | cpuid               =   | ||
| + | | cpuid 2             =   | ||
| + | |||
| + | | isa family          = x86-64  | ||
| + | | isa                 = x86  | ||
| + | | microarch           = Skylake  | ||
| + | | platform            = Purley  | ||
| + | | chipset             = Lewisburg  | ||
| + | | core name           = Skylake SP  | ||
| + | | core family         =   | ||
| + | | core model          =   | ||
| + | | core stepping       = H0  | ||
| + | | process             = 14 nm  | ||
| + | | transistors         =   | ||
| + | | technology          = CMOS  | ||
| + | | die area            = <!-- XX mm² -->  | ||
| + | | die width           =   | ||
| + | | die length          =   | ||
| + | | word size           = 64 bit  | ||
| + | | core count          =   | ||
| + | | thread count        =   | ||
| + | | max cpus            =   | ||
| + | | max memory          =   | ||
| + | |||
| + | | electrical          =   | ||
| + | | power               =   | ||
| + | | average power       =   | ||
| + | | idle power          =   | ||
| + | | v core              =   | ||
| + | | v core tolerance    = <!-- OR ... -->  | ||
| + | | v core min          =   | ||
| + | | v core max          =   | ||
| + | | v io                =   | ||
| + | | v io tolerance      =   | ||
| + | | v io 2              = <!-- OR ... -->  | ||
| + | | v io 3              =   | ||
| + | | sdp                 =   | ||
| + | | tdp                 =   | ||
| + | | tdp typical         =   | ||
| + | | ctdp down           =   | ||
| + | | ctdp down frequency =   | ||
| + | | ctdp up             =   | ||
| + | | ctdp up frequency   =   | ||
| + | | temp min            = <!-- use TJ/TC whenever possible instead -->  | ||
| + | | temp max            =   | ||
| + | | tjunc min           = <!-- .. °C -->  | ||
| + | | tjunc max           =   | ||
| + | | tcase min           =   | ||
| + | | tcase max           =   | ||
| + | | tstorage min        =   | ||
| + | | tstorage max        =   | ||
| + | | tambient min        =   | ||
| + | | tambient max        =   | ||
| + | |||
| + | | package module 1    =   | ||
| + | | package module 2    =   | ||
| + | <!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->  | ||
| + | | packaging           = Yes  | ||
| + | | package 0           = FCLGA-3647  | ||
| + | | package 0 type      = LGA  | ||
| + | | package 0 pins      = 3647  | ||
| + | | package 0 pitch     =   | ||
| + | | package 0 width     =   | ||
| + | | package 0 length    =   | ||
| + | | package 0 height    =   | ||
| + | | socket 0            = LGA-3647  | ||
| + | | socket 0 type       = LGA  | ||
| + | }}  | ||
Revision as of 00:48, 10 May 2017
Facts about "Xeon Gold 6142M  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | Xeon Gold 6142M - Intel#io + | 
| base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + | 
| chipset | Lewisburg + | 
| clock multiplier | 26 + | 
| core count | 16 + | 
| core family | 6 + | 
| core name | Skylake SP + | 
| core stepping | H0 + | 
| cpuid | 0x50654 + | 
| designer | Intel + | 
| family | Xeon Gold + | 
| first announced | April 25, 2017 + | 
| first launched | July 11, 2017 + | 
| full page name | intel/xeon gold/6142m + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has advanced vector extensions 512 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 + | 
| has intel enhanced speedstep technology | true + | 
| has intel speed shift technology | true + | 
| has intel trusted execution technology | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has locked clock multiplier | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| instance of | microprocessor + | 
| isa | x86-64 + | 
| isa family | x86 + | 
| l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + | 
| l2$ description | 16-way set associative + | 
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + | 
| l3$ description | 11-way set associative + | 
| l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + | 
| ldate | July 11, 2017 + | 
| main image | |
| manufacturer | Intel + | 
| market segment | Server + | 
| max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + | 
| max cpu count | 4 + | 
| max dts temperature | 99 °C + | 
| max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + | 
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + | 
| max memory channels | 6 + | 
| max pcie lanes | 48 + | 
| microarchitecture | Skylake (server) + | 
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + | 
| min dts temperature | 0 °C + | 
| model number | 6142M + | 
| name | Xeon Gold 6142M + | 
| package | FCLGA-3647 + | 
| part number | CD8067303405700 + | 
| platform | Purley + | 
| process | 14 nm (0.014 μm, 1.4e-5 mm) + | 
| release price | $ 5,949.00 (€ 5,354.10, £ 4,818.69, ¥ 614,710.17) + | 
| s-spec | SR3B1 + | 
| s-spec (qs) | QMRW + | 
| series | 6100 + | 
| smp interconnect | UPI + | 
| smp interconnect links | 3 + | 
| smp interconnect rate | 10.4 GT/s + | 
| smp max ways | 4 + | 
| socket | Socket P + and LGA-3647 + | 
| supported memory type | DDR4-2666 + | 
| tdp | 150 W (150,000 mW, 0.201 hp, 0.15 kW) + | 
| technology | CMOS + | 
| thread count | 32 + | 
| turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + | 
| word size | 64 bit (8 octets, 16 nibbles) + |