Semiconductor & Computer Engineering
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Difference between revisions of "last level cache"
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| − | '''Last level cache''' ('''LLC''') refers to the highest-level cache that is usually shared by all the functional units on the chip (e.g. [[core|CPU cores]], [[IGP]], and [[DSP]]). | + | '''Last level cache''' ('''LLC''') refers to the highest-level cache that is usually shared by all the functional units on the chip (e.g. [[core|CPU cores]], [[IGP]], and [[DSP]]) |
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| + | The term can also be used in conjunction with a system whereby the LLC might represent a different hierarchical level of cache depending on the perspective the component in context. For example, in a typical mainstream {{intel|Skylake|l=arch}} model, there are a set of individual cores along with {{intel|Gen9|an integrated graphics unit|l=arch}}. In those microprocessors, each core has a private [[L1$]] and [[L2$]] and the GPU has its own L1, L2, and L3 cache. Therefore from the CPU core perspective, the LLC is effectively an L3 cache whereas from the GPU perspective the LLC is a level 4 cache. | ||
Revision as of 05:07, 27 April 2017
Last level cache (LLC) refers to the highest-level cache that is usually shared by all the functional units on the chip (e.g. CPU cores, IGP, and DSP)
The term can also be used in conjunction with a system whereby the LLC might represent a different hierarchical level of cache depending on the perspective the component in context. For example, in a typical mainstream Skylake model, there are a set of individual cores along with an integrated graphics unit. In those microprocessors, each core has a private L1$ and L2$ and the GPU has its own L1, L2, and L3 cache. Therefore from the CPU core perspective, the LLC is effectively an L3 cache whereas from the GPU perspective the LLC is a level 4 cache.