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Difference between revisions of "intel/atom/z520"
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This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled.
 
This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled.
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 +
== Cache ==
 +
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
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{{cache size
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|l1 cache=56 KiB
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|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=24 KiB
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|l1d break=1x24 KiB
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|l1d desc=6-way set associative
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|l1d policy=write-back
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|l2 cache=512 KiB
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|l2 break=1x512 KiB
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|l2 desc=8-way set associative
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}}
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== Memory controller ==
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This processor has no integrated memory controller.
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== Graphics ==
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This processor has no integrated graphics.
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== Features ==
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{{x86 features
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|real=Yes
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|protected=Yes
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|smm=Yes
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|fpu=Yes
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|x8616=Yes
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|x8632=Yes
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|x8664=No
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|nx=Yes
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|mmx=Yes
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|emmx=Yes
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|sse=Yes
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|sse2=Yes
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|sse3=Yes
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|ssse3=Yes
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|sse41=No
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|sse42=No
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|sse4a=No
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|avx=No
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|avx2=No
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|avx512=No
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|abm=No
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|tbm=No
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|bmi1=No
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|bmi2=No
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|fma3=No
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|fma4=No
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|aes=No
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|rdrand=No
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|sha=No
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|xop=No
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|adx=No
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|clmul=No
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|f16c=No
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|tbt1=No
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|tbt2=No
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|tbmt3=No
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|bpt=No
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|eist=Yes
 +
|sst=No
 +
|flex=No
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|fastmem=No
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|isrt=No
 +
|sba=No
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|mwt=No
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|sipp=No
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|att=No
 +
|ipt=No
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|tsx=No
 +
|txt=No
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|ht=Yes
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|vpro=No
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|vtx=No
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|vtd=No
 +
|ept=No
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|mpx=No
 +
|sgx=No
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|securekey=No
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|osguard=No
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|3dnow=No
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|e3dnow=No
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|smartmp=No
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|powernow=No
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|amdvi=No
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|amdv=No
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|rvi=No
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|smt=No
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|sensemi=No
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|xfr=No
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}}
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== Die Shot ==
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{{see also|intel/microarchitectures/bonnell#Silverthorne|l1=Bonnell § Silverthorne Die}}
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* [[45 nm process]]
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* 9 metal layers
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* 47,212,207 transistors
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* 3.1 mm x 7.8 mm
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* 24.18 mm² die size
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 +
[[File:Silverthorne die shot.jpg|650px]]
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 +
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[[File:Silverthorne die shot (marked).png|650px]]

Revision as of 19:27, 1 April 2017

Template:mpu Z520 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

This processor has a TDP of 2 W when Hyper-Threading is disabled and 2.2 W when enabled.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller

This processor has no integrated memory controller.

Graphics

This processor has no integrated graphics.

Features

Die Shot

See also: Bonnell § Silverthorne Die
  • 45 nm process
  • 9 metal layers
  • 47,212,207 transistors
  • 3.1 mm x 7.8 mm
  • 24.18 mm² die size

Silverthorne die shot.jpg


Silverthorne die shot (marked).png

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Facts about "Atom Z520 - Intel"
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has featureHyper-Threading Technology + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has simultaneous multithreadingtrue +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +